Loading arch/sh/lib64/dbg.c +0 −48 Original line number Diff line number Diff line Loading @@ -246,51 +246,3 @@ void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs) print_dtlb(); print_itlb(); } /* ======================================================================= */ /* ** Depending on <base> scan the MMU, Data or Instruction side ** looking for a valid mapping matching Eaddr & asid. ** Return -1 if not found or the TLB id entry otherwise. ** Note: it works only for 4k pages! */ static unsigned long lookup_mmu_side(unsigned long base, unsigned long Eaddr, unsigned long asid) { regType_t pteH; unsigned long epn; int count; epn = Eaddr & 0xfffff000; for (count = 0; count < MAX_TLBs; count++, base += TLB_STEP) { pteH = getConfigReg(base); if (GET_VALID(pteH)) if ((unsigned long) GET_EPN(pteH) == epn) if ((unsigned long) GET_ASID(pteH) == asid) break; } return ((unsigned long) ((count < MAX_TLBs) ? base : -1)); } unsigned long lookup_dtlb(unsigned long Eaddr) { unsigned long asid = get_asid(); return (lookup_mmu_side((u64) DTLB_BASE, Eaddr, asid)); } unsigned long lookup_itlb(unsigned long Eaddr) { unsigned long asid = get_asid(); return (lookup_mmu_side((u64) ITLB_BASE, Eaddr, asid)); } void print_page(struct page *page) { printk(" page[%p] -> index 0x%lx, count 0x%x, flags 0x%lx\n", page, page->index, page_count(page), page->flags); printk(" address_space = %p, pages =%ld\n", page->mapping, page->mapping->nrpages); } arch/sh/lib64/udelay.c +1 −1 Original line number Diff line number Diff line Loading @@ -33,7 +33,7 @@ void __delay(unsigned long loops) :"0"(loops)); } inline void __const_udelay(unsigned long xloops) void __const_udelay(unsigned long xloops) { __delay(xloops * (HZ * cpu_data[raw_smp_processor_id()].loops_per_jiffy)); } Loading Loading
arch/sh/lib64/dbg.c +0 −48 Original line number Diff line number Diff line Loading @@ -246,51 +246,3 @@ void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs) print_dtlb(); print_itlb(); } /* ======================================================================= */ /* ** Depending on <base> scan the MMU, Data or Instruction side ** looking for a valid mapping matching Eaddr & asid. ** Return -1 if not found or the TLB id entry otherwise. ** Note: it works only for 4k pages! */ static unsigned long lookup_mmu_side(unsigned long base, unsigned long Eaddr, unsigned long asid) { regType_t pteH; unsigned long epn; int count; epn = Eaddr & 0xfffff000; for (count = 0; count < MAX_TLBs; count++, base += TLB_STEP) { pteH = getConfigReg(base); if (GET_VALID(pteH)) if ((unsigned long) GET_EPN(pteH) == epn) if ((unsigned long) GET_ASID(pteH) == asid) break; } return ((unsigned long) ((count < MAX_TLBs) ? base : -1)); } unsigned long lookup_dtlb(unsigned long Eaddr) { unsigned long asid = get_asid(); return (lookup_mmu_side((u64) DTLB_BASE, Eaddr, asid)); } unsigned long lookup_itlb(unsigned long Eaddr) { unsigned long asid = get_asid(); return (lookup_mmu_side((u64) ITLB_BASE, Eaddr, asid)); } void print_page(struct page *page) { printk(" page[%p] -> index 0x%lx, count 0x%x, flags 0x%lx\n", page, page->index, page_count(page), page->flags); printk(" address_space = %p, pages =%ld\n", page->mapping, page->mapping->nrpages); }
arch/sh/lib64/udelay.c +1 −1 Original line number Diff line number Diff line Loading @@ -33,7 +33,7 @@ void __delay(unsigned long loops) :"0"(loops)); } inline void __const_udelay(unsigned long xloops) void __const_udelay(unsigned long xloops) { __delay(xloops * (HZ * cpu_data[raw_smp_processor_id()].loops_per_jiffy)); } Loading