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Commit efa310ba authored by Conor Dooley's avatar Conor Dooley
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riscv: dts: microchip: hook up the mpfs' l2cache



The initial PolarFire SoC devicetree must have been forked off from
the fu540 one prior to the addition of l2cache controller support being
added there. When the controller node was added to mpfs.dtsi, it was
not hooked up to the CPUs & thus sysfs reports an incorrect cache
configuration. Hook it up.

Fixes: 0fa6107e ("RISC-V: Initial DTS for Microchip ICICLE board")
Reviewed-by: default avatarSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: default avatarDaire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 5e757ded
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