Commit f09d2b0b authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Initialize eDP source rates after per-panel VBT parsing 



We'll need to know the VBT panel_type before we can determine the
maximum link rate for eDP. To that end move
intel_dp_set_source_rates() & co. to be called after the per-panel
VBT parsing has been done.

intel_dp_mst_encoder_init() depends on the source rates so we'll
have to do it a bit later as well.

v2: Fix the intel_dp_mst_encoder_init() oops

Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220603165841.15481-1-ville.syrjala@linux.intel.com
parent eb20cf30

drivers/gpu/drm/i915/display/intel_dp.c

+8 −11
Original line number Diff line number Diff line
@@ -2846,9 +2846,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) 
		intel_dp_set_sink_rates(intel_dp);

	intel_dp_set_max_sink_lane_count(intel_dp);



	intel_dp_set_common_rates(intel_dp);

	intel_dp_reset_max_link_params(intel_dp);



	/* Read the eDP DSC DPCD registers */

	if (DISPLAY_VER(dev_priv) >= 10)

		intel_dp_get_dsc_sink_cap(intel_dp);
@@ -5336,11 +5333,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, 
		type = DRM_MODE_CONNECTOR_DisplayPort;

	}



	intel_dp_set_source_rates(intel_dp);

	intel_dp_set_default_sink_rates(intel_dp);

	intel_dp_set_default_max_sink_lane_count(intel_dp);

	intel_dp_set_common_rates(intel_dp);

	intel_dp_reset_max_link_params(intel_dp);



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
@@ -5368,16 +5362,19 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, 
	else

		intel_connector->get_hw_state = intel_connector_get_hw_state;



	/* init MST on ports that can support it */

	intel_dp_mst_encoder_init(dig_port,

				  intel_connector->base.base.id);



	if (!intel_edp_init_connector(intel_dp, intel_connector)) {

		intel_dp_aux_fini(intel_dp);

		intel_dp_mst_encoder_cleanup(dig_port);

		goto fail;

	}



	intel_dp_set_source_rates(intel_dp);

	intel_dp_set_common_rates(intel_dp);

	intel_dp_reset_max_link_params(intel_dp);



	/* init MST on ports that can support it */

	intel_dp_mst_encoder_init(dig_port,

				  intel_connector->base.base.id);



	intel_dp_add_properties(intel_dp, connector);



	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {