Commit f0a339a8 authored by Mohammad Zafar Ziya's avatar Mohammad Zafar Ziya Committed by Alex Deucher
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drm/amdgpu/vcn: Add vcn and jpeg ver 2.6 ras register definition 



Adding vcn and jpeg ver 2.6 ras register definition

Signed-off-by: default avatarMohammad Zafar Ziya <Mohammadzafar.ziya@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent edd08fa1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

+13 −0
Original line number Diff line number Diff line
@@ -988,4 +988,17 @@ 
#define mmMDM_WIG_PIPE_BUSY_BASE_IDX                                                                   1





/* VCN 2_6_0 regs */

#define mmUVD_RAS_VCPU_VCODEC_STATUS                           0x0057

#define mmUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX                  1

#define mmUVD_RAS_MMSCH_FATAL_ERROR                            0x0058

#define mmUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX                   1





/* JPEG 2_6_0 regs */

#define mmUVD_RAS_JPEG0_STATUS                                 0x0059

#define mmUVD_RAS_JPEG0_STATUS_BASE_IDX                        1

#define mmUVD_RAS_JPEG1_STATUS                                 0x005a

#define mmUVD_RAS_JPEG1_STATUS_BASE_IDX                        1



#endif

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

+24 −0
Original line number Diff line number Diff line
@@ -3606,4 +3606,28 @@ 
#define UVD_LMI_CRC3__CRC32_MASK                                                                              0xFFFFFFFFL





/* VCN 2_6_0 UVD_RAS_VCPU_VCODEC_STATUS */

#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT          0x0

#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT          0x1f

#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK            0x7FFFFFFFL

#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK            0x80000000L



/* VCN 2_6_0 UVD_RAS_MMSCH_FATAL_ERROR */

#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT           0x0

#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT           0x1f

#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK             0x7FFFFFFFL

#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK             0x80000000L



/* JPEG 2_6_0 UVD_RAS_JPEG0_STATUS */

#define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT                0x0

#define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT                0x1f

#define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK                  0x7FFFFFFFL

#define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK                  0x80000000L



/* JPEG 2_6_0 UVD_RAS_JPEG1_STATUS */

#define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT                0x0

#define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT                0x1f

#define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK                  0x7FFFFFFFL

#define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK                  0x80000000L



#endif