Commit f1b2d06d authored by Alim Akhtar's avatar Alim Akhtar Committed by Vinod Koul
Browse files

phy: samsung-ufs: add support for FSD ufs phy driver 



Adds support for Tesla Full Self-Driving (FSD) ufs phy driver.
This SoC has different cdr lock status offset.

Signed-off-by: default avatarBharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: default avatarChanho Park <chanho61.park@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220610104119.66401-4-alim.akhtar@samsung.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent e313216b

drivers/phy/samsung/Makefile

+1 −0
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@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o 
phy-exynos-ufs-y			+= phy-samsung-ufs.o

phy-exynos-ufs-y			+= phy-exynos7-ufs.o

phy-exynos-ufs-y			+= phy-exynosautov9-ufs.o

phy-exynos-ufs-y			+= phy-fsd-ufs.o

obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-exynos-usb2.o

phy-exynos-usb2-y			+= phy-samsung-usb2.o

phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o

drivers/phy/samsung/phy-fsd-ufs.c

0 → 100644
+58 −0
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// SPDX-License-Identifier: GPL-2.0-only

/*

 * UFS PHY driver data for FSD SoC

 *

 * Copyright (C) 2022 Samsung Electronics Co., Ltd.

 *

 */

#include "phy-samsung-ufs.h"



#define FSD_EMBEDDED_COMBO_PHY_CTRL	0x724

#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1

#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)

#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x6e



static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {

	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),

	PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),

	PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),

	PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),

	END_UFS_PHY_CFG

};



/* Calibration for HS mode series A/B */

static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {

	END_UFS_PHY_CFG

};



/* Calibration for HS mode series A/B atfer PMC */

static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {

	END_UFS_PHY_CFG

};



static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {

	[CFG_PRE_INIT]		= fsd_pre_init_cfg,

	[CFG_PRE_PWR_HS]	= fsd_pre_pwr_hs_cfg,

	[CFG_POST_PWR_HS]	= fsd_post_pwr_hs_cfg,

};



const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {

	.cfgs = fsd_ufs_phy_cfgs,

	.isol = {

		.offset = FSD_EMBEDDED_COMBO_PHY_CTRL,

		.mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,

		.en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,

	},

	.has_symbol_clk = 0,

	.cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,

};

drivers/phy/samsung/phy-samsung-ufs.c

+3 −0
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@@ -358,6 +358,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = { 
	}, {

		.compatible = "samsung,exynosautov9-ufs-phy",

		.data = &exynosautov9_ufs_phy,

	}, {

		.compatible = "tesla,fsd-ufs-phy",

		.data = &fsd_ufs_phy,

	},

	{},

};

drivers/phy/samsung/phy-samsung-ufs.h

+1 −0
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@@ -145,5 +145,6 @@ static inline void samsung_ufs_phy_ctrl_isol( 


extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;

extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;

extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;



#endif /* _PHY_SAMSUNG_UFS_ */