Unverified Commit f2023385 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Palmer Dabbelt
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dt-bindings: riscv: cpus: drop unneeded quotes 



Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230609140706.64623-1-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent ca7473cb

Documentation/devicetree/bindings/riscv/cpus.yaml

+3 −3
Original line number Original line Diff line number Diff line
@@ -61,7 +61,7 @@ properties: 
      hart.  These values originate from the RISC-V Privileged

      hart.  These values originate from the RISC-V Privileged

      Specification document, available from

      Specification document, available from

      https://riscv.org/specifications/

      https://riscv.org/specifications/

    $ref: "/schemas/types.yaml#/definitions/string"

    $ref: /schemas/types.yaml#/definitions/string

    enum:

    enum:

      - riscv,sv32

      - riscv,sv32

      - riscv,sv39

      - riscv,sv39
@@ -95,7 +95,7 @@ properties: 
      While the isa strings in ISA specification are case

      While the isa strings in ISA specification are case

      insensitive, letters in the riscv,isa string must be all

      insensitive, letters in the riscv,isa string must be all

      lowercase.

      lowercase.

    $ref: "/schemas/types.yaml#/definitions/string"

    $ref: /schemas/types.yaml#/definitions/string

    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$

    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$





  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here

  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
@@ -120,7 +120,7 @@ properties: 
      - interrupt-controller

      - interrupt-controller





  cpu-idle-states:

  cpu-idle-states:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

    items:

      maxItems: 1

      maxItems: 1

    description: |

    description: |