Commit f217d94f authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

arm64: dts: microchip: add missing cache properties 

As all level 2 and level 3 caches are unified, add required
cache-unified and cache-level properties to fix warnings like:

  sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property

Link: https://lore.kernel.org/r/20230421223155.115339-1-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 4c84cced

arch/arm64/boot/dts/microchip/sparx5.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ cpu1: cpu@1 { 
		};

		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};