Commit f3c677b9 authored by Forrest Shi's avatar Forrest Shi Committed by Dan Williams
Browse files

fsldma: fix issue of slow dma 



Fixed fsl dma slow issue by initializing dma mode register with
bandwidth control. It boosts dma performance and should works
with 85xx board.

Signed-off-by: default avatarForrest Shi <b29237@freescale.com>
Signed-off-by: default avatarLi Yang <leoli@freescale.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent c989a7fc

drivers/dma/fsldma.c

+4 −2
Original line number Diff line number Diff line
@@ -50,9 +50,11 @@ static void dma_init(struct fsldma_chan *chan) 
		 * EIE - Error interrupt enable

		 * EOSIE - End of segments interrupt enable (basic mode)

		 * EOLNIE - End of links interrupt enable

		 * BWC - Bandwidth sharing among channels

		 */

		DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE

				| FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);

		DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC

				| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE

				| FSL_DMA_MR_EOSIE, 32);

		break;

	case FSL_DMA_IP_83XX:

		/* Set the channel to below modes:

drivers/dma/fsldma.h

+8 −1
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.

 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.

 *

 * Author:

 *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
@@ -36,6 +36,13 @@ 
#define FSL_DMA_MR_DAHE		0x00002000

#define FSL_DMA_MR_SAHE		0x00001000



/*

 * Bandwidth/pause control determines how many bytes a given

 * channel is allowed to transfer before the DMA engine pauses

 * the current channel and switches to the next channel

 */

#define FSL_DMA_MR_BWC         0x08000000



/* Special MR definition for MPC8349 */

#define FSL_DMA_MR_EOTIE	0x00000080

#define FSL_DMA_MR_PRC_RM	0x00000800