Commit f3cd264c authored by Robert Richter's avatar Robert Richter Committed by Dan Williams
Browse files

cxl: Unify debug messages when calling devm_cxl_add_port() 



CXL ports are added in a couple of code paths using devm_cxl_add_port().
Debug messages are individually generated, but are incomplete and
inconsistent. Change this by moving its generation to
devm_cxl_add_port(). This unifies the messages and reduces code
duplication.  Also, generate messages on failure. Use a
__devm_cxl_add_port() wrapper to keep the readability of the error
exits.

Signed-off-by: default avatarRobert Richter <rrichter@amd.com>
Link: https://lore.kernel.org/r/20221018132341.76259-4-rrichter@amd.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 3bb80da5

drivers/cxl/acpi.c

+0 −2
Original line number Diff line number Diff line
@@ -220,7 +220,6 @@ static int add_host_bridge_uport(struct device *match, void *arg) 
	port = devm_cxl_add_port(host, match, dport->component_reg_phys, dport);

	if (IS_ERR(port))

		return PTR_ERR(port);

	dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev));



	return 0;

}
@@ -466,7 +465,6 @@ static int cxl_acpi_probe(struct platform_device *pdev) 
	root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);

	if (IS_ERR(root_port))

		return PTR_ERR(root_port);

	dev_dbg(host, "add: %s\n", dev_name(&root_port->dev));



	rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,

			      add_host_bridge_dport);

drivers/cxl/core/port.c

+39 −12
Original line number Diff line number Diff line
@@ -655,14 +655,8 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, 
	return ERR_PTR(rc);

}



/**

 * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy

 * @host: host device for devm operations

 * @uport: "physical" device implementing this upstream port

 * @component_reg_phys: (optional) for configurable cxl_port instances

 * @parent_dport: next hop up in the CXL memory decode hierarchy

 */

struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,

static struct cxl_port *__devm_cxl_add_port(struct device *host,

					    struct device *uport,

					    resource_size_t component_reg_phys,

					    struct cxl_dport *parent_dport)

{
@@ -702,6 +696,41 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, 
	put_device(dev);

	return ERR_PTR(rc);

}



/**

 * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy

 * @host: host device for devm operations

 * @uport: "physical" device implementing this upstream port

 * @component_reg_phys: (optional) for configurable cxl_port instances

 * @parent_dport: next hop up in the CXL memory decode hierarchy

 */

struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,

				   resource_size_t component_reg_phys,

				   struct cxl_dport *parent_dport)

{

	struct cxl_port *port, *parent_port;



	port = __devm_cxl_add_port(host, uport, component_reg_phys,

				   parent_dport);



	parent_port = parent_dport ? parent_dport->port : NULL;

	if (IS_ERR(port)) {

		dev_dbg(uport, "Failed to add %s%s%s%s: %ld\n",

			dev_name(&port->dev),

			parent_port ? " to " : "",

			parent_port ? dev_name(&parent_port->dev) : "",

			parent_port ? "" : " (root port)",

			PTR_ERR(port));

	} else {

		dev_dbg(uport, "%s added%s%s%s\n",

			dev_name(&port->dev),

			parent_port ? " to " : "",

			parent_port ? dev_name(&parent_port->dev) : "",

			parent_port ? "" : " (root port)");

	}



	return port;

}

EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, CXL);



struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port)
@@ -1147,8 +1176,6 @@ int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd, 
	if (IS_ERR(endpoint))

		return PTR_ERR(endpoint);



	dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));



	rc = cxl_endpoint_autoremove(cxlmd, endpoint);

	if (rc)

		return rc;