Commit f3f45c73 authored by Shiva Kerdel's avatar Shiva Kerdel Committed by Greg Kroah-Hartman
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Staging: ks7010: ks_*: Use the BIT macro for bitwise checks



Changed bit swifting operators to BIT macros (preferred),
This change will also solve the preferred space surrounding
the operator checks.

Signed-off-by: default avatarShiva Kerdel <shiva@exdev.nl>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent bd18762d
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+10 −10
Original line number Diff line number Diff line
@@ -285,16 +285,16 @@ struct ap_info_t {
	uint8_t pad0;	/* +09 */
	uint16_t beacon_period;	/* +10 */
	uint16_t capability;	/* +12 */
#define BSS_CAP_ESS             (1<<0)
#define BSS_CAP_IBSS            (1<<1)
#define BSS_CAP_CF_POLABLE      (1<<2)
#define BSS_CAP_CF_POLL_REQ     (1<<3)
#define BSS_CAP_PRIVACY         (1<<4)
#define BSS_CAP_SHORT_PREAMBLE  (1<<5)
#define BSS_CAP_PBCC            (1<<6)
#define BSS_CAP_CHANNEL_AGILITY (1<<7)
#define BSS_CAP_SHORT_SLOT_TIME (1<<10)
#define BSS_CAP_DSSS_OFDM       (1<<13)
#define BSS_CAP_ESS             BIT(0)
#define BSS_CAP_IBSS            BIT(1)
#define BSS_CAP_CF_POLABLE      BIT(2)
#define BSS_CAP_CF_POLL_REQ     BIT(3)
#define BSS_CAP_PRIVACY         BIT(4)
#define BSS_CAP_SHORT_PREAMBLE  BIT(5)
#define BSS_CAP_PBCC            BIT(6)
#define BSS_CAP_CHANNEL_AGILITY BIT(7)
#define BSS_CAP_SHORT_SLOT_TIME BIT(10)
#define BSS_CAP_DSSS_OFDM       BIT(13)
	uint8_t frame_type;	/* +14 */
	uint8_t ch_info;	/* +15 */
#define FRAME_TYPE_BEACON	0x80
+15 −15
Original line number Diff line number Diff line
@@ -85,23 +85,23 @@ enum {
};

/* SME flag */
#define SME_MODE_SET	    (1<<0)
#define SME_RTS             (1<<1)
#define SME_FRAG            (1<<2)
#define SME_WEP_FLAG        (1<<3)
#define SME_WEP_INDEX       (1<<4)
#define SME_WEP_VAL1        (1<<5)
#define SME_WEP_VAL2        (1<<6)
#define SME_WEP_VAL3        (1<<7)
#define SME_WEP_VAL4        (1<<8)
#define SME_MODE_SET	    BIT(0)
#define SME_RTS             BIT(1)
#define SME_FRAG            BIT(2)
#define SME_WEP_FLAG        BIT(3)
#define SME_WEP_INDEX       BIT(4)
#define SME_WEP_VAL1        BIT(5)
#define SME_WEP_VAL2        BIT(6)
#define SME_WEP_VAL3        BIT(7)
#define SME_WEP_VAL4        BIT(8)
#define SME_WEP_VAL_MASK    (SME_WEP_VAL1 | SME_WEP_VAL2 | SME_WEP_VAL3 | SME_WEP_VAL4)
#define SME_RSN             (1<<9)
#define SME_RSN_MULTICAST   (1<<10)
#define SME_RSN_UNICAST	    (1<<11)
#define SME_RSN_AUTH	    (1<<12)
#define SME_RSN             BIT(9)
#define SME_RSN_MULTICAST   BIT(10)
#define SME_RSN_UNICAST	    BIT(11)
#define SME_RSN_AUTH	    BIT(12)

#define SME_AP_SCAN         (1<<13)
#define SME_MULTICAST       (1<<14)
#define SME_AP_SCAN         BIT(13)
#define SME_MULTICAST       BIT(14)

/* SME Event */
enum {