Loading drivers/video/s3fb.c +1 −1 Original line number Diff line number Diff line Loading @@ -552,7 +552,7 @@ static int s3fb_set_par(struct fb_info *info) } vga_wcrt(NULL, 0x3A, 0x35); svga_wattr(0x33, 0x00); svga_wattr(par->state.vgabase, 0x33, 0x00); if (info->var.vmode & FB_VMODE_DOUBLE) svga_wcrt_mask(0x09, 0x80, 0x80); Loading drivers/video/svgalib.c +9 −9 Original line number Diff line number Diff line Loading @@ -102,14 +102,14 @@ void svga_set_default_atc_regs(void) /* All standard ATC registers (AR00 - AR14) */ for (count = 0; count <= 0xF; count ++) svga_wattr(count, count); svga_wattr(NULL, count, count); svga_wattr(VGA_ATC_MODE, 0x01); /* svga_wattr(VGA_ATC_MODE, 0x41); */ svga_wattr(VGA_ATC_OVERSCAN, 0x00); svga_wattr(VGA_ATC_PLANE_ENABLE, 0x0F); svga_wattr(VGA_ATC_PEL, 0x00); svga_wattr(VGA_ATC_COLOR_PAGE, 0x00); svga_wattr(NULL, VGA_ATC_MODE, 0x01); /* svga_wattr(NULL, VGA_ATC_MODE, 0x41); */ svga_wattr(NULL, VGA_ATC_OVERSCAN, 0x00); svga_wattr(NULL, VGA_ATC_PLANE_ENABLE, 0x0F); svga_wattr(NULL, VGA_ATC_PEL, 0x00); svga_wattr(NULL, VGA_ATC_COLOR_PAGE, 0x00); vga_r(NULL, 0x3DA); vga_w(NULL, VGA_ATT_W, 0x20); Loading Loading @@ -159,8 +159,8 @@ void svga_set_textmode_vga_regs(void) vga_r(NULL, 0x3DA); vga_w(NULL, VGA_ATT_W, 0x00); svga_wattr(0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ svga_wattr(0x13, 0x08); /* Horizontal Pixel Panning Register */ svga_wattr(NULL, 0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ svga_wattr(NULL, 0x13, 0x08); /* Horizontal Pixel Panning Register */ vga_r(NULL, 0x3DA); vga_w(NULL, VGA_ATT_W, 0x20); Loading include/linux/svga.h +4 −4 Original line number Diff line number Diff line Loading @@ -67,11 +67,11 @@ struct svga_pll { /* Write a value to the attribute register */ static inline void svga_wattr(u8 index, u8 data) static inline void svga_wattr(void __iomem *regbase, u8 index, u8 data) { inb(VGA_IS1_RC); outb(index, VGA_ATT_IW); outb(data, VGA_ATT_W); vga_r(regbase, VGA_IS1_RC); vga_w(regbase, VGA_ATT_IW, index); vga_w(regbase, VGA_ATT_W, data); } /* Write a value to a sequence register with a mask */ Loading Loading
drivers/video/s3fb.c +1 −1 Original line number Diff line number Diff line Loading @@ -552,7 +552,7 @@ static int s3fb_set_par(struct fb_info *info) } vga_wcrt(NULL, 0x3A, 0x35); svga_wattr(0x33, 0x00); svga_wattr(par->state.vgabase, 0x33, 0x00); if (info->var.vmode & FB_VMODE_DOUBLE) svga_wcrt_mask(0x09, 0x80, 0x80); Loading
drivers/video/svgalib.c +9 −9 Original line number Diff line number Diff line Loading @@ -102,14 +102,14 @@ void svga_set_default_atc_regs(void) /* All standard ATC registers (AR00 - AR14) */ for (count = 0; count <= 0xF; count ++) svga_wattr(count, count); svga_wattr(NULL, count, count); svga_wattr(VGA_ATC_MODE, 0x01); /* svga_wattr(VGA_ATC_MODE, 0x41); */ svga_wattr(VGA_ATC_OVERSCAN, 0x00); svga_wattr(VGA_ATC_PLANE_ENABLE, 0x0F); svga_wattr(VGA_ATC_PEL, 0x00); svga_wattr(VGA_ATC_COLOR_PAGE, 0x00); svga_wattr(NULL, VGA_ATC_MODE, 0x01); /* svga_wattr(NULL, VGA_ATC_MODE, 0x41); */ svga_wattr(NULL, VGA_ATC_OVERSCAN, 0x00); svga_wattr(NULL, VGA_ATC_PLANE_ENABLE, 0x0F); svga_wattr(NULL, VGA_ATC_PEL, 0x00); svga_wattr(NULL, VGA_ATC_COLOR_PAGE, 0x00); vga_r(NULL, 0x3DA); vga_w(NULL, VGA_ATT_W, 0x20); Loading Loading @@ -159,8 +159,8 @@ void svga_set_textmode_vga_regs(void) vga_r(NULL, 0x3DA); vga_w(NULL, VGA_ATT_W, 0x00); svga_wattr(0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ svga_wattr(0x13, 0x08); /* Horizontal Pixel Panning Register */ svga_wattr(NULL, 0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ svga_wattr(NULL, 0x13, 0x08); /* Horizontal Pixel Panning Register */ vga_r(NULL, 0x3DA); vga_w(NULL, VGA_ATT_W, 0x20); Loading
include/linux/svga.h +4 −4 Original line number Diff line number Diff line Loading @@ -67,11 +67,11 @@ struct svga_pll { /* Write a value to the attribute register */ static inline void svga_wattr(u8 index, u8 data) static inline void svga_wattr(void __iomem *regbase, u8 index, u8 data) { inb(VGA_IS1_RC); outb(index, VGA_ATT_IW); outb(data, VGA_ATT_W); vga_r(regbase, VGA_IS1_RC); vga_w(regbase, VGA_ATT_IW, index); vga_w(regbase, VGA_ATT_W, data); } /* Write a value to a sequence register with a mask */ Loading