Commit f6d06f33 authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
Browse files

ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9 



For supporting single image on all Tegra series, we need to skip some HW
support code for Cortex-A9 only.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 4b3e2eda

arch/arm/mach-tegra/sleep.S

+5 −3
Original line number Diff line number Diff line
@@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu) 
	isb

#ifdef CONFIG_CACHE_L2X0

	/* Disable L2 cache */

	mov32	r4, TEGRA_ARM_PERIF_BASE + 0x3000

	mov	r5, #0

	str	r5, [r4, #L2X0_CTRL]

	check_cpu_part_num 0xc09, r9, r10

	movweq	r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)

	movteq	r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)

	moveq	r5, #0

	streq	r5, [r4, #L2X0_CTRL]

#endif

	mov	pc, r0

ENDPROC(tegra_shut_off_mmu)

arch/arm/mach-tegra/sleep.h

+18 −6
Original line number Diff line number Diff line
@@ -70,19 +70,31 @@ 
	movt	\reg, #:upper16:\val

.endm



/* Marco to check CPU part num */

.macro check_cpu_part_num part_num, tmp1, tmp2

	mrc	p15, 0, \tmp1, c0, c0, 0

	ubfx	\tmp1, \tmp1, #4, #12

	mov32	\tmp2, \part_num

	cmp	\tmp1, \tmp2

.endm



/* Macro to exit SMP coherency. */

.macro exit_smp, tmp1, tmp2

	mrc	p15, 0, \tmp1, c1, c0, 1	@ ACTLR

	bic	\tmp1, \tmp1, #(1<<6) | (1<<0)	@ clear ACTLR.SMP | ACTLR.FW

	mcr	p15, 0, \tmp1, c1, c0, 1	@ ACTLR

	isb

	cpu_id	\tmp1

	mov	\tmp1, \tmp1, lsl #2

	mov	\tmp2, #0xf

	mov	\tmp2, \tmp2, lsl \tmp1

	mov32	\tmp1, TEGRA_ARM_PERIF_VIRT + 0xC

	str	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU

#ifdef CONFIG_HAVE_ARM_SCU

	check_cpu_part_num 0xc09, \tmp1, \tmp2

	mrceq	p15, 0, \tmp1, c0, c0, 5

	andeq	\tmp1, \tmp1, #0xF

	moveq	\tmp1, \tmp1, lsl #2

	moveq	\tmp2, #0xf

	moveq	\tmp2, \tmp2, lsl \tmp1

	ldreq	\tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)

	streq	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU

	dsb

#endif

.endm



/* Macro to check Tegra revision */