Commit f6f8bb59 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/gfx9: switch to amdgpu_gfx_rlc_init_microcode 



switch to common helper to initialize rlc firmware
for gfx9

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5b415212

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −103
Original line number Diff line number Diff line
@@ -1091,27 +1091,6 @@ static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 
	kfree(adev->gfx.rlc.register_list_format);

}



static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)

{

	const struct rlc_firmware_header_v2_1 *rlc_hdr;



	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;

	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);

	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);

	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);

	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);

	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);

	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);

	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);

	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);

	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);

	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);

	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);

	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);

	adev->gfx.rlc.reg_list_format_direct_reg_list_length =

			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);

}



static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)

{

	adev->gfx.me_fw_write_wait = false;
@@ -1353,11 +1332,7 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 
{

	char fw_name[30];

	int err;

	struct amdgpu_firmware_info *info = NULL;

	const struct common_firmware_header *header = NULL;

	const struct rlc_firmware_header_v2_0 *rlc_hdr;

	unsigned int *tmp = NULL;

	unsigned int i = 0;

	uint16_t version_major;

	uint16_t version_minor;

	uint32_t smu_version;
@@ -1386,88 +1361,13 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 
	if (err)

		goto out;

	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);

	if (err)

		goto out;

	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;



	version_major = le16_to_cpu(rlc_hdr->header.header_version_major);

	version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);

	if (version_major == 2 && version_minor == 1)

		adev->gfx.rlc.is_rlc_v2_1 = true;



	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);

	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);

	adev->gfx.rlc.save_and_restore_offset =

			le32_to_cpu(rlc_hdr->save_and_restore_offset);

	adev->gfx.rlc.clear_state_descriptor_offset =

			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);

	adev->gfx.rlc.avail_scratch_ram_locations =

			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);

	adev->gfx.rlc.reg_restore_list_size =

			le32_to_cpu(rlc_hdr->reg_restore_list_size);

	adev->gfx.rlc.reg_list_format_start =

			le32_to_cpu(rlc_hdr->reg_list_format_start);

	adev->gfx.rlc.reg_list_format_separate_start =

			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);

	adev->gfx.rlc.starting_offsets_start =

			le32_to_cpu(rlc_hdr->starting_offsets_start);

	adev->gfx.rlc.reg_list_format_size_bytes =

			le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);

	adev->gfx.rlc.reg_list_size_bytes =

			le32_to_cpu(rlc_hdr->reg_list_size_bytes);

	adev->gfx.rlc.register_list_format =

			kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +

				adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);

	if (!adev->gfx.rlc.register_list_format) {

		err = -ENOMEM;

		goto out;

	}



	tmp = (unsigned int *)((uintptr_t)rlc_hdr +

			le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));

	for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)

		adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);



	adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;



	tmp = (unsigned int *)((uintptr_t)rlc_hdr +

			le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));

	for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)

		adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);



	if (adev->gfx.rlc.is_rlc_v2_1)

		gfx_v9_0_init_rlc_ext_microcode(adev);



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];

		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;

		info->fw = adev->gfx.rlc_fw;

		header = (const struct common_firmware_header *)info->fw->data;

		adev->firmware.fw_size +=

			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);



		if (adev->gfx.rlc.is_rlc_v2_1 &&

		    adev->gfx.rlc.save_restore_list_cntl_size_bytes &&

		    adev->gfx.rlc.save_restore_list_gpm_size_bytes &&

		    adev->gfx.rlc.save_restore_list_srm_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];

			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);



			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];

			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);



			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];

			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);

		}

	}



	err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);

out:

	if (err) {

		dev_err(adev->dev,