Commit f7fdc4db authored by Chanho Park's avatar Chanho Park Committed by Vinod Koul
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phy: samsung: exynosautov9-ufs: correct TSRV register configurations



For exynos auto v9's UFS MPHY, We should use 0x50 offset of TSRV register
configurations. So, it must be

s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG_AUTOV9/g

Fixes: d6451924 ("phy: samsung-ufs: support exynosauto ufs phy driver")
Signed-off-by: default avatarChanho Park <chanho61.park@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220603050536.61957-1-chanho61.park@samsung.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 8567abec
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+9 −9
Original line number Diff line number Diff line
@@ -31,22 +31,22 @@ static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = {
	PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
	PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),

	PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),

	END_UFS_PHY_CFG,
};

/* Calibration for HS mode series A/B */
static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
	PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY),
	PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY),
	PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY),
	PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
	PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
	PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),

	PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
	PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
	PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
	PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
				PWR_MODE_HS_G3_SER_B),
	PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
	PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),

	END_UFS_PHY_CFG,
};