Commit f8522fc8 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvc0: fix suspend/resume of PGRAPH/PCOPYn 



We need the physical VRAM address in vinst, even for objects mapped into
a vm, as the gpuobj suspend/resume code uses PMEM to access the object.

Previously, vinst was overloaded to mean "VRAM address" for !VM objects,
and "VM address" for VM objects, causing the wrong data to be accessed
during suspend/resume.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent aba99a84

drivers/gpu/drm/nouveau/nouveau_drv.h

+4 −3
Original line number Diff line number Diff line
@@ -176,9 +176,10 @@ struct nouveau_gpuobj { 
	uint32_t flags;



	u32 size;

	u32 pinst;

	u32 cinst;

	u64 vinst;

	u32 pinst;	/* PRAMIN BAR offset */

	u32 cinst;	/* Channel offset */

	u64 vinst;	/* VRAM address */

	u64 linst;	/* VM address */



	uint32_t engine;

	uint32_t class;

drivers/gpu/drm/nouveau/nv50_instmem.c

+1 −2
Original line number Diff line number Diff line
@@ -305,7 +305,6 @@ struct nv50_gpuobj_node { 
	u32 align;

};





int

nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)

{
@@ -345,7 +344,7 @@ nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align) 
		}



		nouveau_vm_map(&node->chan_vma, node->vram);

		gpuobj->vinst = node->chan_vma.offset;

		gpuobj->linst = node->chan_vma.offset;

	}



	gpuobj->size = size;

drivers/gpu/drm/nouveau/nvc0_copy.c

+2 −2
Original line number Diff line number Diff line
@@ -54,8 +54,8 @@ nvc0_copy_context_new(struct nouveau_channel *chan, int engine) 
	if (ret)

		return ret;



	nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->vinst));

	nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(ctx->vinst));

	nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->linst));

	nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(ctx->linst));

	dev_priv->engine.instmem.flush(dev);



	chan->engctx[engine] = ctx;

drivers/gpu/drm/nouveau/nvc0_graph.c

+10 −10
Original line number Diff line number Diff line
@@ -131,27 +131,27 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan) 




	nv_wo32(grch->mmio, i++ * 4, 0x00408004);

	nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);

	nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);

	nv_wo32(grch->mmio, i++ * 4, 0x00408008);

	nv_wo32(grch->mmio, i++ * 4, 0x80000018);



	nv_wo32(grch->mmio, i++ * 4, 0x0040800c);

	nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);

	nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);

	nv_wo32(grch->mmio, i++ * 4, 0x00408010);

	nv_wo32(grch->mmio, i++ * 4, 0x80000000);



	nv_wo32(grch->mmio, i++ * 4, 0x00418810);

	nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12);

	nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->linst >> 12);

	nv_wo32(grch->mmio, i++ * 4, 0x00419848);

	nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12);

	nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->linst >> 12);



	nv_wo32(grch->mmio, i++ * 4, 0x00419004);

	nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);

	nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);

	nv_wo32(grch->mmio, i++ * 4, 0x00419008);

	nv_wo32(grch->mmio, i++ * 4, 0x00000000);



	nv_wo32(grch->mmio, i++ * 4, 0x00418808);

	nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);

	nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);

	nv_wo32(grch->mmio, i++ * 4, 0x0041880c);

	nv_wo32(grch->mmio, i++ * 4, 0x80000018);
@@ -197,8 +197,8 @@ nvc0_graph_context_new(struct nouveau_channel *chan, int engine) 
	if (ret)

		goto error;



	nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4);

	nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst));

	nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->linst) | 4);

	nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->linst));

	pinstmem->flush(dev);



	if (!priv->grctx_vals) {
@@ -213,8 +213,8 @@ nvc0_graph_context_new(struct nouveau_channel *chan, int engine) 
	nv_wo32(grctx, 0xf4, 0);

	nv_wo32(grctx, 0xf8, 0);

	nv_wo32(grctx, 0x10, grch->mmio_nr);

	nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));

	nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));

	nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst));

	nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst));

	nv_wo32(grctx, 0x1c, 1);

	nv_wo32(grctx, 0x20, 0);

	nv_wo32(grctx, 0x28, 0);