Unverified Commit f8632adc authored by Rander Wang's avatar Rander Wang Committed by Mark Brown
Browse files

ASoC: SOF: Intel: add d0i3_offset in chip_info 



MTL has different d0i3 offset compared to cavs platforms.
Use d0i3_offset to unify the setting.

Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: default avatarRander Wang <rander.wang@intel.com>
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221107164154.21925-3-pierre-louis.bossart@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 09e3c1d3

sound/soc/sof/intel/apl.c

+1 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ const struct sof_intel_dsp_desc apl_chip_info = { 
	.rom_init_timeout	= 150,

	.ssp_count = APL_SSP_COUNT,

	.ssp_base_offset = APL_SSP_BASE_OFFSET,

	.d0i3_offset = SOF_HDA_VS_D0I3C,

	.quirks = SOF_INTEL_PROCEN_FMT_QUIRK,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

sound/soc/sof/intel/cnl.c

+2 −0
Original line number Diff line number Diff line
@@ -456,6 +456,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = { 
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,

	.d0i3_offset = SOF_HDA_VS_D0I3C,

	.check_sdw_irq	= hda_common_check_sdw_irq,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,
@@ -488,6 +489,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = { 
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,

	.d0i3_offset = SOF_HDA_VS_D0I3C,

	.check_sdw_irq	= hda_common_check_sdw_irq,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

sound/soc/sof/intel/icl.c

+1 −0
Original line number Diff line number Diff line
@@ -180,6 +180,7 @@ const struct sof_intel_dsp_desc icl_chip_info = { 
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,

	.d0i3_offset = SOF_HDA_VS_D0I3C,

	.check_sdw_irq	= hda_common_check_sdw_irq,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

sound/soc/sof/intel/mtl.c

+1 −0
Original line number Diff line number Diff line
@@ -684,6 +684,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = { 
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE_ACE,

	.sdw_alh_base = SDW_ALH_BASE_ACE,

	.d0i3_offset = MTL_HDA_VS_D0I3C,

	.check_sdw_irq = mtl_dsp_check_sdw_irq,

	.check_ipc_irq = mtl_dsp_check_ipc_irq,

	.cl_init = mtl_dsp_cl_init,

sound/soc/sof/intel/shim.h

+1 −0
Original line number Diff line number Diff line
@@ -182,6 +182,7 @@ struct sof_intel_dsp_desc { 
	int ssp_base_offset;		/* base address of the SSPs */

	u32 sdw_shim_base;

	u32 sdw_alh_base;

	u32 d0i3_offset;

	u32 quirks;

	enum sof_intel_hw_ip_version hw_ip_version;

	bool (*check_sdw_irq)(struct snd_sof_dev *sdev);