Commit f98bf9ee authored by Guo-Feng Fan's avatar Guo-Feng Fan Committed by Kalle Valo
Browse files

rtw88: 8822c: reorder macro position according to the register number 



This patch doesn't change logic at all, just a refactor patch.

1. Move BIT MASK and BIT definition along with the register definition
2. Remove redundant definition
3. Align macros with Tab key

Signed-off-by: default avatarGuo-Feng Fan <vincent_fann@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20210419003748.3224-2-pkshih@realtek.com
parent a926c025

drivers/net/wireless/realtek/rtw88/rtw8822c.c

+8 −8
Original line number Diff line number Diff line
@@ -1095,13 +1095,13 @@ static void rtw8822c_pa_bias(struct rtw_dev *rtwdev) 
		if (pg_pa_bias == EFUSE_READ_FAIL)

			return;

		pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);

		rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_2G_MASK, pg_pa_bias);

		rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_2G_MASK, pg_pa_bias);

	}

	for (path = 0; path < rtwdev->hal.rf_path_num; path++) {

		rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path],

					 &pg_pa_bias);

		pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);

		rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_5G_MASK, pg_pa_bias);

		rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_5G_MASK, pg_pa_bias);

	}

}
@@ -2546,9 +2546,9 @@ static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev) 
		rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);

		rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));

		if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)

			rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);

			rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);

		else

			rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);

			rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);

		rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);

		rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);

	}
@@ -2566,11 +2566,11 @@ static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path) 


	rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);

	rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);

	rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0);

	rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0);

	rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);



	if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {

		rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1);

		rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1);

		rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);

	} else {

		rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
@@ -3317,9 +3317,9 @@ static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev) 
		rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,

				 0x8 | (path << 1));

		if (dpk_info->dpk_band == RTW_BAND_2G)

			rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);

			rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);

		else

			rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);

			rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);



		rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);

drivers/net/wireless/realtek/rtw88/rtw8822c.h

+140 −135
Original line number Diff line number Diff line
@@ -164,7 +164,6 @@ const struct rtw_table name ## _tbl = { \ 


#define REG_ANAPARLDO_POW_MAC	0x0029

#define BIT_LDOE25_PON		BIT(0)



#define XCAP_MASK		GENMASK(6, 0)

#define CFO_TRK_ENABLE_TH	20

#define CFO_TRK_STOP_TH		10
@@ -180,14 +179,17 @@ const struct rtw_table name ## _tbl = { \ 
#define REG_SBD			0x88c

#define BITS_SUBTUNE		GENMASK(15, 12)

#define REG_DYMTHMIN		0x8a4



#define REG_TXBWCTL		0x9b0

#define REG_TXCLK		0x9b4



#define REG_SCOTRK		0xc30

#define REG_MRCM		0xc38

#define REG_AGCSWSH		0xc44

#define REG_ANTWTPD		0xc54

#define REG_PT_CHSMO		0xcbc

#define BIT_PT_OPT		BIT(21)



#define REG_ORITXCODE		0x1800

#define REG_3WIRE		0x180c

#define BIT_3WIRE_TX_EN		BIT(0)
@@ -202,6 +204,7 @@ const struct rtw_table name ## _tbl = { \ 
#define REG_DCKA_I_1		0x18c0

#define REG_DCKA_Q_0		0x18d8

#define REG_DCKA_Q_1		0x18dc



#define REG_CCKSB		0x1a00

#define REG_RXCCKSEL		0x1a04

#define REG_BGCTRL		0x1a14
@@ -222,7 +225,36 @@ const struct rtw_table name ## _tbl = { \ 
#define REG_TXF7		0x1ab0

#define REG_CCK_SOURCE		0x1abc

#define BIT_NBI_EN		BIT(30)



#define REG_NCTL0		0x1b00

#define BIT_SUBPAGE		GENMASK(3, 0)

#define REG_DPD_CTL0_S0		0x1b04

#define BIT_GS_PWSF		GENMASK(27, 0)

#define REG_DPD_CTL1_S0		0x1b08

#define BIT_DPD_EN		BIT(31)

#define REG_IQKSTAT		0x1b10

#define REG_IQK_CTL1		0x1b20

#define BIT_BYPASS_DPD		BIT(25)

#define BIT_TX_CFIR		GENMASK(31, 30)

#define REG_DPD_LUT0		0x1b44

#define BIT_GLOSS_DB		GENMASK(14, 12)

#define REG_DPD_CTL0_S1		0x1b5c

#define REG_DPD_CTL1_S1		0x1b60

#define REG_DPD_AGC		0x1b67

#define REG_DPD_CTL0		0x1bb4

#define REG_R_CONFIG		0x1bcc

#define BIT_INNER_LB		BIT(21)

#define BIT_IQ_SWITCH		GENMASK(5, 0)

#define REG_RXSRAM_CTL		0x1bd4

#define BIT_RPT_SEL		GENMASK(20, 16)

#define BIT_DPD_CLK		GENMASK(7, 4)

#define REG_DPD_CTL11		0x1be4

#define REG_DPD_CTL12		0x1be8

#define REG_DPD_CTL15		0x1bf4

#define REG_DPD_CTL16		0x1bf8

#define REG_STAT_RPT		0x1bfc

#define BIT_RPT_DGAIN		GENMASK(27, 16)



#define REG_TXANT		0x1c28

#define REG_ENCCK		0x1c3c

#define BIT_CCK_BLK_EN		BIT(1)
@@ -230,6 +262,7 @@ const struct rtw_table name ## _tbl = { \ 
#define REG_CCAMSK		0x1c80

#define REG_RSTB		0x1c90

#define BIT_RSTB_3WIRE		BIT(8)



#define REG_RX_BREAK		0x1d2c

#define BIT_COM_RX_GCK_EN	BIT(31)

#define REG_RXFNCTL		0x1d30
@@ -240,6 +273,7 @@ const struct rtw_table name ## _tbl = { \ 
#define REG_CCKPATH		0x1e5c

#define REG_CNT_CTRL		0x1eb4

#define BIT_ALL_CNT_RST		BIT(25)



#define REG_OFDM_FACNT		0x2d00

#define REG_OFDM_FACNT1		0x2d04

#define REG_OFDM_FACNT2		0x2d08
@@ -248,6 +282,7 @@ const struct rtw_table name ## _tbl = { \ 
#define REG_OFDM_FACNT5		0x2d20

#define REG_RPT_CIP		0x2d9c

#define REG_OFDM_TXCNT		0x2de0



#define REG_ORITXCODE2		0x4100

#define REG_3WIRE2		0x410c

#define REG_ANAPAR_B		0x4130
@@ -258,86 +293,56 @@ const struct rtw_table name ## _tbl = { \ 
#define REG_DCKB_Q_1		0x41dc



#define RF_MODE_TRXAGC		0x00

#define BIT_RXAGC		GENMASK(9, 5)

#define BIT_TXAGC		GENMASK(4, 0)

#define RF_RXAGC_OFFSET		0x19

#define RF_BW_TRXBB		0x1a

#define BIT_BW_TXBB		GENMASK(14, 12)

#define BIT_BW_RXBB		GENMASK(11, 10)

#define RF_TX_GAIN_OFFSET	0x55

#define BIT_BB_GAIN		GENMASK(18, 14)

#define BIT_RF_GAIN		GENMASK(4, 2)

#define RF_TX_GAIN		0x56

#define BIT_GAIN_TXBB		GENMASK(4, 0)

#define RF_PA			0x60

#define RF_PABIAS_2G_MASK	GENMASK(15, 12)

#define RF_PABIAS_5G_MASK	GENMASK(19, 16)

#define RF_TXA_LB_SW		0x63

#define BIT_TXA_LB_ATT		GENMASK(15, 14)

#define BIT_LB_SW		GENMASK(13, 12)

#define BIT_LB_ATT		GENMASK(4, 2)

#define RF_RXG_GAIN		0x87

#define BIT_RXG_GAIN		BIT(18)

#define RF_RXA_MIX_GAIN		0x8a

#define BIT_RXA_MIX_GAIN	GENMASK(4, 3)

#define RF_EXT_TIA_BW		0x8f

#define RF_DEBUG		0xde



#define REG_NCTL0		0x1b00

#define REG_DPD_CTL0_S0		0x1b04

#define REG_DPD_CTL1_S0		0x1b08

#define REG_IQK_CTL1		0x1b20

#define REG_DPD_LUT0		0x1b44

#define REG_DPD_CTL0_S1		0x1b5c

#define REG_DPD_LUT3		0x1b60

#define REG_DPD_CTL1_S1		0x1b60

#define REG_DPD_AGC		0x1b67

#define REG_DPD_CTL0		0x1bb4

#define REG_R_CONFIG		0x1bcc

#define REG_RXSRAM_CTL		0x1bd4

#define REG_DPD_CTL11		0x1be4

#define REG_DPD_CTL12		0x1be8

#define REG_DPD_CTL15		0x1bf4

#define REG_DPD_CTL16		0x1bf8

#define REG_STAT_RPT		0x1bfc



#define BIT_EXT_TIA_BW		BIT(1)

#define BIT_DE_TRXBW		BIT(2)

#define BIT_DE_TX_GAIN		BIT(16)

#define BIT_RXG_GAIN		BIT(18)

#define BIT_DE_PWR_TRIM		BIT(19)

#define BIT_INNER_LB		BIT(21)

#define BIT_BYPASS_DPD		BIT(25)

#define BIT_DPD_EN		BIT(31)

#define BIT_SUBPAGE		GENMASK(3, 0)

#define BIT_TXAGC		GENMASK(4, 0)

#define BIT_GAIN_TXBB		GENMASK(4, 0)

#define BIT_LB_ATT		GENMASK(4, 2)

#define BIT_RXA_MIX_GAIN	GENMASK(4, 3)

#define BIT_IQ_SWITCH		GENMASK(5, 0)

#define BIT_DPD_CLK		GENMASK(7, 4)

#define BIT_RXAGC		GENMASK(9, 5)

#define BIT_BW_RXBB		GENMASK(11, 10)

#define BIT_LB_SW		GENMASK(13, 12)

#define BIT_BW_TXBB		GENMASK(14, 12)

#define BIT_GLOSS_DB		GENMASK(14, 12)

#define BIT_TXA_LB_ATT		GENMASK(15, 14)

#define BIT_TX_OFFSET_VAL	GENMASK(18, 14)

#define BIT_RPT_SEL		GENMASK(20, 16)

#define BIT_GS_PWSF		GENMASK(27, 0)

#define BIT_RPT_DGAIN		GENMASK(27, 16)

#define BIT_TX_CFIR		GENMASK(31, 30)

#define BIT_DE_TX_GAIN		BIT(16)

#define BIT_DE_TRXBW		BIT(2)



#define PPG_THERMAL_A 0x1ef

#define PPG_THERMAL_B		0x1b0

#define RF_THEMAL_MASK		GENMASK(19, 16)

#define PPG_2GL_TXAB 0x1d4

#define PPG_2GM_TXAB 0x1ee

#define PPG_2GH_TXAB		0x1d2

#define PPG_2G_A_MASK		GENMASK(3, 0)

#define PPG_2G_B_MASK		GENMASK(7, 4)

#define PPG_5GL1_TXA 0x1ec

#define PPG_5GL2_TXA 0x1e8

#define PPG_5GM1_TXA 0x1e4

#define PPG_5GM2_TXA 0x1e0

#define PPG_5GH1_TXA 0x1dc

#define PPG_5GL1_TXB 0x1eb

#define PPG_5GL2_TXB 0x1e7

#define PPG_5GM1_TXB 0x1e3

#define PPG_5GM2_TXB 0x1df

#define PPG_5GH1_TXB 0x1db

#define PPG_5G_MASK GENMASK(4, 0)

#define PPG_PABIAS_2GA 0x1d6

#define PPG_2GL_TXAB		0x1d4

#define PPG_PABIAS_2GB		0x1d5

#define PPG_PABIAS_5GA 0x1d8

#define PPG_PABIAS_5GB 0x1d7

#define PPG_PABIAS_2GA		0x1d6

#define PPG_PABIAS_MASK		GENMASK(3, 0)

#define RF_PABIAS_2G_MASK GENMASK(15, 12)

#define RF_PABIAS_5G_MASK GENMASK(19, 16)



#define PPG_PABIAS_5GB		0x1d7

#define PPG_PABIAS_5GA		0x1d8

#define PPG_5G_MASK		GENMASK(4, 0)

#define PPG_5GH1_TXB		0x1db

#define PPG_5GH1_TXA		0x1dc

#define PPG_5GM2_TXB		0x1df

#define PPG_5GM2_TXA		0x1e0

#define PPG_5GM1_TXB		0x1e3

#define PPG_5GM1_TXA		0x1e4

#define PPG_5GL2_TXB		0x1e7

#define PPG_5GL2_TXA		0x1e8

#define PPG_5GL1_TXB		0x1eb

#define PPG_5GL1_TXA		0x1ec

#define PPG_2GM_TXAB		0x1ee

#define PPG_THERMAL_A		0x1ef

#endif