Commit f9c84ae5 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: correct programming of ih_chicken for Arcturus 



ih_chicken is a register that is not allowed to access by driver
in the L0 security policy.
psp bl need to enable field to allow driver to use physical
bus address for ih ring on secure part.

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarSnow Zhang <snow.zhang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5ce40fd8

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+10 −1
Original line number Diff line number Diff line
@@ -219,7 +219,7 @@ static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 
static int vega10_ih_irq_init(struct amdgpu_device *adev)

{

	struct amdgpu_ih_ring *ih;

	u32 ih_rb_cntl;

	u32 ih_rb_cntl, ih_chicken;

	int ret = 0;

	u32 tmp;
@@ -247,6 +247,15 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 
		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

	}



	if (adev->asic_type == CHIP_ARCTURUS &&

		adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {

		if (adev->irq.ih.use_bus_addr) {

			ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);

			ih_chicken |= 0x00000010;

			WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);

		}

	}



	/* set the writeback address whether it's enabled or not */

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,

		     lower_32_bits(ih->wptr_addr));