Commit fa0321ba authored by Florian Fainelli's avatar Florian Fainelli Committed by Krzysztof Kozlowski
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dt-bindings: memory-controller: Document Broadcom STB MEMC 



Document the Broadcom STB memory controller which is a trivial binding
for now with a set of compatible strings and single register.

Since we introduce this binding, the section in
Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt is removed
and this binding is referenced instead.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
[krzk: correct path in brcm,brcmstb.txt]
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220812222533.2428033-2-f.fainelli@gmail.com
parent 568035b0

Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt

+2 −9
Original line number Diff line number Diff line
@@ -187,15 +187,8 @@ Required properties: 
Sequencer DRAM parameters and control registers. Used for Self-Refresh

Power-Down (SRPD), among other things.



Required properties:

- compatible     : should contain one of these

	"brcm,brcmstb-memc-ddr-rev-b.2.1"

	"brcm,brcmstb-memc-ddr-rev-b.2.2"

	"brcm,brcmstb-memc-ddr-rev-b.2.3"

	"brcm,brcmstb-memc-ddr-rev-b.3.0"

	"brcm,brcmstb-memc-ddr-rev-b.3.1"

	"brcm,brcmstb-memc-ddr"

- reg            : the MEMC DDR register range

See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a

full list of supported compatible strings and properties.



Example:

Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Memory controller (MEMC) for Broadcom STB



maintainers:

  - Florian Fainelli <f.fainelli@gmail.com>



properties:

  compatible:

    items:

      - enum:

          - brcm,brcmstb-memc-ddr-rev-b.1.x

          - brcm,brcmstb-memc-ddr-rev-b.2.0

          - brcm,brcmstb-memc-ddr-rev-b.2.1

          - brcm,brcmstb-memc-ddr-rev-b.2.2

          - brcm,brcmstb-memc-ddr-rev-b.2.3

          - brcm,brcmstb-memc-ddr-rev-b.2.5

          - brcm,brcmstb-memc-ddr-rev-b.2.6

          - brcm,brcmstb-memc-ddr-rev-b.2.7

          - brcm,brcmstb-memc-ddr-rev-b.2.8

          - brcm,brcmstb-memc-ddr-rev-b.3.0

          - brcm,brcmstb-memc-ddr-rev-b.3.1

          - brcm,brcmstb-memc-ddr-rev-c.1.0

          - brcm,brcmstb-memc-ddr-rev-c.1.1

          - brcm,brcmstb-memc-ddr-rev-c.1.2

          - brcm,brcmstb-memc-ddr-rev-c.1.3

          - brcm,brcmstb-memc-ddr-rev-c.1.4

      - const: brcm,brcmstb-memc-ddr



  reg:

    maxItems: 1



  clock-frequency:

    description: DDR PHY frequency in Hz



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    memory-controller@9902000 {

        compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr";

        reg = <0x9902000 0x600>;

        clock-frequency = <2133000000>;

    };