Commit fbb6b31a authored by Nick Forrington's avatar Nick Forrington Committed by Arnaldo Carvalho de Melo
Browse files

perf vendors events arm64: Arm Cortex-A55 

Add PMU events for Arm Cortex-A55
Add corresponding common events
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a55.json

which is based on PMU event descriptions from the Arm Cortex-A55 Technical
Reference Manual.

Common event data based on:
https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json

which is based on PMU event descriptions found in the Arm Architecture
Reference Manual:
https://developer.arm.com/documentation/ddi0487/

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json



which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Signed-off-by: default avatarNick Forrington <nick.forrington@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220520181455.340344-4-nick.forrington@arm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent b5d03547

tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json

0 → 100644
+59 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "BR_MIS_PRED"

    },

    {

        "ArchStdEvent": "BR_PRED"

    },

    {

        "ArchStdEvent": "BR_IMMED_SPEC"

    },

    {

        "ArchStdEvent": "BR_RETURN_SPEC"

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC"

    },

    {

        "PublicDescription": "Predicted conditional branch executed.This event counts when any branch which can be predicted by the conditional predictor is retired. This event still counts when branch prediction is disabled due to the MMU being off",

        "EventCode": "0xC9",

        "EventName": "BR_COND_PRED",

        "BriefDescription": "Predicted conditional branch executed.This event counts when any branch which can be predicted by the conditional predictor is retired. This event still counts when branch prediction is disabled due to the MMU being off"

    },

    {

        "PublicDescription": "Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicted for either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off",

        "EventCode": "0xCA",

        "EventName": "BR_INDIRECT_MIS_PRED",

        "BriefDescription": "Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicted for either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off"

    },

    {

        "PublicDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",

        "EventCode": "0xCB",

        "EventName": "BR_INDIRECT_ADDR_MIS_PRED",

        "BriefDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"

    },

    {

        "PublicDescription": "Conditional branch mis-predicted.This event counts when any branch which can be predicted by the conditional predictor is retired, and has mis-predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches which correctly predicted the condition but mis-predicted on the address do not count this event",

        "EventCode": "0xCC",

        "EventName": "BR_COND_MIS_PRED",

        "BriefDescription": "Conditional branch mis-predicted.This event counts when any branch which can be predicted by the conditional predictor is retired, and has mis-predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches which correctly predicted the condition but mis-predicted on the address do not count this event"

    },

    {

        "PublicDescription": "Indirect branch with predicted address executed.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",

        "EventCode": "0xCD",

        "EventName": "BR_INDIRECT_ADDR_PRED",

        "BriefDescription": "Indirect branch with predicted address executed.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"

    },

    {

        "PublicDescription": "Procedure return with predicted address executed.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",

        "EventCode": "0xCE",

        "EventName": "BR_RETURN_ADDR_PRED",

        "BriefDescription": "Procedure return with predicted address executed.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"

    },

    {

        "PublicDescription": "Procedure return mis-predicted due to address mis-compare.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",

        "EventCode": "0xCF",

        "EventName": "BR_RETURN_ADDR_MIS_PRED",

        "BriefDescription": "Procedure return mis-predicted due to address mis-compare.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json

0 → 100644
+17 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "CPU_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS"

    },

    {

        "ArchStdEvent": "BUS_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json

0 → 100644
+188 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L1D_TLB"

    },

    {

        "ArchStdEvent": "L1I_TLB"

    },

    {

        "ArchStdEvent": "L3D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L3D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L3D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L2D_TLB"

    },

    {

        "ArchStdEvent": "DTLB_WALK"

    },

    {

        "ArchStdEvent": "ITLB_WALK"

    },

    {

        "ArchStdEvent": "LL_CACHE_RD"

    },

    {

        "ArchStdEvent": "LL_CACHE_MISS_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L3D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L3D_CACHE_REFILL_RD"

    },

    {

        "PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to both distinguish hardware vs software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented",

        "EventCode": "0xC0",

        "EventName": "L3D_CACHE_REFILL_PREFETCH",

        "BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to both distinguish hardware vs software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented"

    },

    {

        "PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented",

        "EventCode": "0xC1",

        "EventName": "L2D_CACHE_REFILL_PREFETCH",

        "BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented"

    },

    {

        "PublicDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",

        "EventCode": "0xC2",

        "EventName": "L1D_CACHE_REFILL_PREFETCH",

        "BriefDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"

    },

    {

        "PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache",

        "EventCode": "0xC3",

        "EventName": "L2D_WS_MODE",

        "BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache"

    },

    {

        "PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each entry into write-streaming mode",

        "EventCode": "0xC4",

        "EventName": "L1D_WS_MODE_ENTRY",

        "BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each entry into write-streaming mode"

    },

    {

        "PublicDescription": "Level 1 data cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L1 D-cache",

        "EventCode": "0xC5",

        "EventName": "L1D_WS_MODE",

        "BriefDescription": "Level 1 data cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L1 D-cache"

    },

    {

        "PublicDescription": "Level 3 cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache",

        "EventCode": "0xC7",

        "EventName": "L3D_WS_MODE",

        "BriefDescription": "Level 3 cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache"

    },

    {

        "PublicDescription": "Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled",

        "EventCode": "0xD0",

        "EventName": "L2D_LLWALK_TLB",

        "BriefDescription": "Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled"

    },

    {

        "PublicDescription": "Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled",

        "EventCode": "0xD1",

        "EventName": "L2D_LLWALK_TLB_REFILL",

        "BriefDescription": "Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled"

    },

    {

        "PublicDescription": "Level 2 TLB level-2 walk cache access.This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled",

        "EventCode": "0xD2",

        "EventName": "L2D_L2WALK_TLB",

        "BriefDescription": "Level 2 TLB level-2 walk cache access.This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled"

    },

    {

        "PublicDescription": "Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled",

        "EventCode": "0xD3",

        "EventName": "L2D_L2WALK_TLB_REFILL",

        "BriefDescription": "Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled"

    },

    {

        "PublicDescription": "Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count",

        "EventCode": "0xD4",

        "EventName": "L2D_S2_TLB",

        "BriefDescription": "Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count"

    },

    {

        "PublicDescription": "Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count",

        "EventCode": "0xD5",

        "EventName": "L2D_S2_TLB_REFILL",

        "BriefDescription": "Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count"

    },

    {

        "PublicDescription": "Level 2 cache stash dropped.This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request",

        "EventCode": "0xD6",

        "EventName": "L2D_CACHE_STASH_DROPPED",

        "BriefDescription": "Level 2 cache stash dropped.This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json

0 → 100644
+20 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "EXC_TAKEN"

    },

    {

        "ArchStdEvent": "MEMORY_ERROR"

    },

    {

        "ArchStdEvent": "EXC_IRQ"

    },

    {

        "ArchStdEvent": "EXC_FIQ"

    },

    {

        "PublicDescription": "Predecode error",

        "EventCode": "0xC6",

        "EventName": "PREDECODE_ERROR",

        "BriefDescription": "Predecode error"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json

0 → 100644
+65 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "SW_INCR"

    },

    {

        "ArchStdEvent": "LD_RETIRED"

    },

    {

        "ArchStdEvent": "ST_RETIRED"

    },

    {

        "ArchStdEvent": "INST_RETIRED"

    },

    {

        "ArchStdEvent": "EXC_RETURN"

    },

    {

        "ArchStdEvent": "CID_WRITE_RETIRED"

    },

    {

        "ArchStdEvent": "PC_WRITE_RETIRED"

    },

    {

        "ArchStdEvent": "BR_IMMED_RETIRED"

    },

    {

        "ArchStdEvent": "BR_RETURN_RETIRED"

    },

    {

        "ArchStdEvent": "INST_SPEC"

    },

    {

        "ArchStdEvent": "TTBR_WRITE_RETIRED"

    },

    {

        "ArchStdEvent": "BR_RETIRED"

    },

    {

        "ArchStdEvent": "BR_MIS_PRED_RETIRED"

    },

    {

        "ArchStdEvent": "LD_SPEC"

    },

    {

        "ArchStdEvent": "ST_SPEC"

    },

    {

        "ArchStdEvent": "LDST_SPEC"

    },

    {

        "ArchStdEvent": "DP_SPEC"

    },

    {

        "ArchStdEvent": "ASE_SPEC"

    },

    {

        "ArchStdEvent": "VFP_SPEC"

    },

    {

        "ArchStdEvent": "PC_WRITE_SPEC"

    },

    {

        "ArchStdEvent": "CRYPTO_SPEC"

    }

]