Commit fcb68dfd authored by Krishna Manikandan's avatar Krishna Manikandan Committed by Bjorn Andersson
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arm64: dts: qcom: sc7280: add display dt nodes 



Add mdss and mdp DT nodes for sc7280.

Signed-off-by: default avatarKrishna Manikandan <quic_mkrishn@quicinc.com>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarSankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1640361793-26486-2-git-send-email-quic_sbillaka@quicinc.com
parent bb59462e

arch/arm64/boot/dts/qcom/sc7280.dtsi

+90 −0
Original line number Diff line number Diff line
@@ -2779,6 +2779,96 @@ dispcc: clock-controller@af00000 { 
			#power-domain-cells = <1>;

		};



		mdss: display-subsystem@ae00000 {

			compatible = "qcom,sc7280-mdss";

			reg = <0 0x0ae00000 0 0x1000>;

			reg-names = "mdss";



			power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;



			clocks = <&gcc GCC_DISP_AHB_CLK>,

				 <&dispcc DISP_CC_MDSS_AHB_CLK>,

				<&dispcc DISP_CC_MDSS_MDP_CLK>;

			clock-names = "iface",

				      "ahb",

				      "core";



			assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;

			assigned-clock-rates = <300000000>;



			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <1>;



			interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;

			interconnect-names = "mdp0-mem";



			iommus = <&apps_smmu 0x900 0x402>;



			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			status = "disabled";



			mdss_mdp: display-controller@ae01000 {

				compatible = "qcom,sc7280-dpu";

				reg = <0 0x0ae01000 0 0x8f030>,

					<0 0x0aeb0000 0 0x2008>;

				reg-names = "mdp", "vbif";



				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

					<&gcc GCC_DISP_SF_AXI_CLK>,

					<&dispcc DISP_CC_MDSS_AHB_CLK>,

					<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

					<&dispcc DISP_CC_MDSS_MDP_CLK>,

					<&dispcc DISP_CC_MDSS_VSYNC_CLK>;

				clock-names = "bus",

					      "nrt_bus",

					      "iface",

					      "lut",

					      "core",

					      "vsync";

				assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,

						<&dispcc DISP_CC_MDSS_VSYNC_CLK>,

						<&dispcc DISP_CC_MDSS_AHB_CLK>;

				assigned-clock-rates = <300000000>,

							<19200000>,

							<19200000>;

				operating-points-v2 = <&mdp_opp_table>;

				power-domains = <&rpmhpd SC7280_CX>;



				interrupt-parent = <&mdss>;

				interrupts = <0>;



				status = "disabled";



				mdp_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-200000000 {

						opp-hz = /bits/ 64 <200000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-300000000 {

						opp-hz = /bits/ 64 <300000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-380000000 {

						opp-hz = /bits/ 64 <380000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-506666667 {

						opp-hz = /bits/ 64 <506666667>;

						required-opps = <&rpmhpd_opp_nom>;

					};

				};

			};

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sc7280-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x30000>;