Commit fde7dc63 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull mailbox updates from Jassi Brar:

 - stm32: race fix by adding a spinlock

 - mhu: trim included headers

 - omap: add support for K3 SoCs

 - imx: Irq disable fix

 - bcm: tidy up extracting driver data

 - tegra: make resume 'noirq'

 - api: fix error handling

* tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: handle failed named mailbox channel request
  mailbox: tegra: avoid resume NULL mailboxes
  mailbox: tegra: hsp: add noirq resume
  mailbox: bcm-flexrm-mailbox: using dev_get_drvdata directly
  mailbox: imx: Clear GIEn bit at shutdown
  mailbox: omap: Add support for TI K3 SoCs
  dt-bindings: mailbox: omap: Update bindings for TI K3 SoCs
  mailbox: arm_mhu: reorder header inclusion and drop unneeded ones
  mailbox: stm32_ipcc: add spinlock to fix channels concurrent access
parents a1240cf7 25777e57
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+50 −9
Original line number Original line Diff line number Diff line
OMAP2+ Mailbox Driver
OMAP2+ and K3 Mailbox
=====================
=====================


The OMAP mailbox hardware facilitates communication between different processors
The OMAP mailbox hardware facilitates communication between different processors
@@ -7,7 +7,7 @@ various processor subsystems and is connected on an interconnect bus. The
communication is achieved through a set of registers for message storage and
communication is achieved through a set of registers for message storage and
interrupt configuration registers.
interrupt configuration registers.


Each mailbox IP block has a certain number of h/w fifo queues and output
Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
interrupt lines. An output interrupt line is routed to an interrupt controller
interrupt lines. An output interrupt line is routed to an interrupt controller
within a processor subsystem, and there can be more than one line going to a
within a processor subsystem, and there can be more than one line going to a
specific processor's interrupt controller. The interrupt line connections are
specific processor's interrupt controller. The interrupt line connections are
@@ -23,12 +23,16 @@ All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
instance. DRA7xx has multiple instances with different number of h/w fifo queues
instance. DRA7xx has multiple instances with different number of h/w fifo queues
and interrupt lines between different instances. The interrupt lines can also be
and interrupt lines between different instances. The interrupt lines can also be
routed to different processor sub-systems on DRA7xx as they are routed through
routed to different processor sub-systems on DRA7xx as they are routed through
the Crossbar, a kind of interrupt router/multiplexer.
the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
SoCs has each of these instances form a cluster and combine multiple clusters
into a single IP block present within the Main NavSS. The interrupt lines from
all these clusters are multiplexed and routed to different processor subsystems
over a limited number of common interrupt output lines of an Interrupt Router.


Mailbox Device Node:
Mailbox Device Node:
====================
====================
A Mailbox device node is used to represent a Mailbox IP instance within a SoC.
A Mailbox device node is used to represent a Mailbox IP instance/cluster within
The sub-mailboxes are represented as child nodes of this parent node.
a SoC. The sub-mailboxes are represented as child nodes of this parent node.


Required properties:
Required properties:
--------------------
--------------------
@@ -37,12 +41,12 @@ Required properties:
			    "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
			    "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
			    "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
			    "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
						   AM43xx and DRA7xx SoCs
						   AM43xx and DRA7xx SoCs
			    "ti,am654-mailbox" for K3 AM65x and J721E SoCs
- reg:			Contains the mailbox register address range (base
- reg:			Contains the mailbox register address range (base
			address and length)
			address and length)
- interrupts:		Contains the interrupt information for the mailbox
- interrupts:		Contains the interrupt information for the mailbox
			device. The format is dependent on which interrupt
			device. The format is dependent on which interrupt
			controller the OMAP device uses
			controller the Mailbox device uses
- ti,hwmods:		Name of the hwmod associated with the mailbox
- #mbox-cells:		Common mailbox binding property to identify the number
- #mbox-cells:		Common mailbox binding property to identify the number
			of cells required for the mailbox specifier. Should be
			of cells required for the mailbox specifier. Should be
			1
			1
@@ -50,6 +54,23 @@ Required properties:
			device can interrupt
			device can interrupt
- ti,mbox-num-fifos:	Number of h/w fifo queues within the mailbox IP block
- ti,mbox-num-fifos:	Number of h/w fifo queues within the mailbox IP block


SoC-specific Required properties:
---------------------------------
The following are mandatory properties for the OMAP architecture based SoCs
only:
- ti,hwmods:		Name of the hwmod associated with the mailbox. This
			should be defined in the mailbox node only if the node
			is not defined as a child node of a corresponding sysc
			interconnect node.

The following are mandatory properties for the K3 AM65x and J721E SoCs only:
- interrupt-parent:	Should contain a phandle to the TI-SCI interrupt
			controller node that is used to dynamically program
			the interrupt routes between the IP and the main GIC
			controllers. See the following binding for additional
			details,
			Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt

Child Nodes:
Child Nodes:
============
============
A child node is used for representing the actual sub-mailbox device that is
A child node is used for representing the actual sub-mailbox device that is
@@ -98,7 +119,7 @@ to be used by the client user.
Example:
Example:
--------
--------


/* OMAP4 */
1. /* OMAP4 */
mailbox: mailbox@4a0f4000 {
mailbox: mailbox@4a0f4000 {
	compatible = "ti,omap4-mailbox";
	compatible = "ti,omap4-mailbox";
	reg = <0x4a0f4000 0x200>;
	reg = <0x4a0f4000 0x200>;
@@ -123,7 +144,7 @@ dsp {
	...
	...
};
};


/* AM33xx */
2. /* AM33xx */
mailbox: mailbox@480c8000 {
mailbox: mailbox@480c8000 {
	compatible = "ti,omap4-mailbox";
	compatible = "ti,omap4-mailbox";
	reg = <0x480C8000 0x200>;
	reg = <0x480C8000 0x200>;
@@ -137,3 +158,23 @@ mailbox: mailbox@480c8000 {
		ti,mbox-rx = <0 0 3>;
		ti,mbox-rx = <0 0 3>;
	};
	};
};
};

3. /* AM65x */
&cbass_main {
	cbass_main_navss: interconnect0 {
		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
			interrupts = <164 0>;

			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
				ti,mbox-tx = <1 0 0>;
				ti,mbox-rx = <0 0 0>;
			};
		};
	};
};
+1 −1
Original line number Original line Diff line number Diff line
@@ -54,7 +54,7 @@ config ARMADA_37XX_RWTM_MBOX


config OMAP2PLUS_MBOX
config OMAP2PLUS_MBOX
	tristate "OMAP2+ Mailbox framework support"
	tristate "OMAP2+ Mailbox framework support"
	depends on ARCH_OMAP2PLUS
	depends on ARCH_OMAP2PLUS || ARCH_K3
	help
	help
	  Mailbox implementation for OMAP family chips with hardware for
	  Mailbox implementation for OMAP family chips with hardware for
	  interprocessor communication involving DSP, IVA1.0 and IVA2 in
	  interprocessor communication involving DSP, IVA1.0 and IVA2 in
+4 −7
Original line number Original line Diff line number Diff line
@@ -5,16 +5,13 @@
 * Author: Jassi Brar <jaswinder.singh@linaro.org>
 * Author: Jassi Brar <jaswinder.singh@linaro.org>
 */
 */


#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/amba/bus.h>
#include <linux/mailbox_controller.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>


#define INTR_STAT_OFS	0x0
#define INTR_STAT_OFS	0x0
#define INTR_SET_OFS	0x8
#define INTR_SET_OFS	0x8
+2 −4
Original line number Original line Diff line number Diff line
@@ -1163,8 +1163,7 @@ static int flexrm_process_completions(struct flexrm_ring *ring)


static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)
static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)
{
{
	struct platform_device *pdev = to_platform_device(file->private);
	struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
	struct flexrm_mbox *mbox = platform_get_drvdata(pdev);


	/* Write config in file */
	/* Write config in file */
	flexrm_write_config_in_seqfile(mbox, file);
	flexrm_write_config_in_seqfile(mbox, file);
@@ -1174,8 +1173,7 @@ static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)


static int flexrm_debugfs_stats_show(struct seq_file *file, void *offset)
static int flexrm_debugfs_stats_show(struct seq_file *file, void *offset)
{
{
	struct platform_device *pdev = to_platform_device(file->private);
	struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
	struct flexrm_mbox *mbox = platform_get_drvdata(pdev);


	/* Write stats in file */
	/* Write stats in file */
	flexrm_write_stats_in_seqfile(mbox, file);
	flexrm_write_stats_in_seqfile(mbox, file);
+2 −2
Original line number Original line Diff line number Diff line
@@ -217,8 +217,8 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
	if (cp->type == IMX_MU_TYPE_TXDB)
	if (cp->type == IMX_MU_TYPE_TXDB)
		tasklet_kill(&cp->txdb_tasklet);
		tasklet_kill(&cp->txdb_tasklet);


	imx_mu_xcr_rmw(priv, 0,
	imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx) |
		   IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx));
		       IMX_MU_xCR_RIEn(cp->idx) | IMX_MU_xCR_GIEn(cp->idx));


	free_irq(priv->irq, chan);
	free_irq(priv->irq, chan);
}
}
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