Commit fe52ece8 authored by Sakari Ailus's avatar Sakari Ailus Committed by Mauro Carvalho Chehab
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media: ccs-pll: Fix condition for pre-PLL divider lower bound 



The lower bound of the pre-PLL divider was calculated based on OP SYS
clock frequency which is also affected by the OP SYS clock divider. This
is wrong. The right clock frequency is that of the PLL output clock.

Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent cab27256

drivers/media/i2c/ccs-pll.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -459,7 +459,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, 
		max_t(uint16_t, min_op_pre_pll_clk_div,

		max_t(uint16_t, min_op_pre_pll_clk_div,

		      clk_div_even_up(

		      clk_div_even_up(

			      DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,

			      DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,

					   op_lim_bk->max_sys_clk_freq_hz)));

					   op_lim_fr->max_pll_op_clk_freq_hz)));

	dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",

	dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",

		min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);

		min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);