Commit fea905d4 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amd/powerplay: set SOCCLK DPM for sienna_cichlid 



Support for SOCCLK DPM for sienna_cichlid.
Use feature mask to control DPM for sienna_cichlid.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9ad9c8ac

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

+11 −3
Original line number Diff line number Diff line
@@ -42,7 +42,8 @@ 
#define FEATURE_MASK(feature) (1ULL << feature)

#define SMC_DPM_FEATURE ( \

	FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \

	FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))

	FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \

	FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))



#define MSG_MAP(msg, index) \

	[SMU_MSG_##msg] = {1, (index)}
@@ -259,13 +260,20 @@ static int 
sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,

				  uint32_t *feature_mask, uint32_t num)

{

	struct amdgpu_device *adev = smu->adev;



	if (num > 2)

		return -EINVAL;



	memset(feature_mask, 0, sizeof(uint32_t) * num);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)

				| FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT);



	if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);



	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);



	return 0;

}