Commit ff474acc authored by Sakari Ailus's avatar Sakari Ailus Committed by Mauro Carvalho Chehab
Browse files

media: ccs-pll: Fix link frequency for C-PHY 



The highest fundamental frequency signal for C-PHY is half of the symbol
rate which is similar to D-PHY. Take this into account in ccs-pll.

Also remove the outdated comment.

Fixes: 8030aa4f ("media: ccs-pll: Add C-PHY support")
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 896111dc

drivers/media/i2c/ccs-pll.c

+1 −7
Original line number Diff line number Diff line
@@ -772,14 +772,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, 


	switch (pll->bus_type) {

	case CCS_PLL_BUS_TYPE_CSI2_DPHY:

		/* CSI transfers 2 bits per clock per lane; thus times 2 */

		op_sys_clk_freq_hz_sdr = pll->link_freq * 2

			* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?

			   1 : pll->csi2.lanes);

		break;

	case CCS_PLL_BUS_TYPE_CSI2_CPHY:

		op_sys_clk_freq_hz_sdr =

			pll->link_freq

		op_sys_clk_freq_hz_sdr = pll->link_freq * 2

			* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?

			   1 : pll->csi2.lanes);

		break;