Commit ffcdf473 authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Thomas Bogendoerfer
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mips: ralink: rt288x: remove clock related code 



A properly clock driver for ralink SoCs has been added. Hence there is no
need to have clock related code in 'arch/mips/ralink' folder anymore.

Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 6f3b1558

arch/mips/include/asm/mach-ralink/rt288x.h

+0 −10
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 
#define SYSC_REG_CHIP_NAME1		0x04

#define SYSC_REG_CHIP_ID		0x0c

#define SYSC_REG_SYSTEM_CONFIG		0x10

#define SYSC_REG_CLKCFG			0x30



#define RT2880_CHIP_NAME0		0x38325452

#define RT2880_CHIP_NAME1		0x20203038
@@ -27,15 +26,6 @@ 
#define CHIP_ID_ID_SHIFT		8

#define CHIP_ID_REV_MASK		0xff



#define SYSTEM_CONFIG_CPUCLK_SHIFT	20

#define SYSTEM_CONFIG_CPUCLK_MASK	0x3

#define SYSTEM_CONFIG_CPUCLK_250	0x0

#define SYSTEM_CONFIG_CPUCLK_266	0x1

#define SYSTEM_CONFIG_CPUCLK_280	0x2

#define SYSTEM_CONFIG_CPUCLK_300	0x3



#define CLKCFG_SRAM_CS_N_WDT		BIT(9)



#define RT2880_SDRAM_BASE		0x08000000

#define RT2880_MEM_SIZE_MIN		2

#define RT2880_MEM_SIZE_MAX		128

arch/mips/ralink/rt288x.c

+0 −31
Original line number Diff line number Diff line
@@ -21,37 +21,6 @@ 


static struct ralink_soc_info *soc_info_ptr;



void __init ralink_clk_init(void)

{

	unsigned long cpu_rate, wmac_rate = 40000000;

	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);

	t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);



	switch (t) {

	case SYSTEM_CONFIG_CPUCLK_250:

		cpu_rate = 250000000;

		break;

	case SYSTEM_CONFIG_CPUCLK_266:

		cpu_rate = 266666667;

		break;

	case SYSTEM_CONFIG_CPUCLK_280:

		cpu_rate = 280000000;

		break;

	case SYSTEM_CONFIG_CPUCLK_300:

		cpu_rate = 300000000;

		break;

	}



	ralink_clk_add("cpu", cpu_rate);

	ralink_clk_add("300100.timer", cpu_rate / 2);

	ralink_clk_add("300120.watchdog", cpu_rate / 2);

	ralink_clk_add("300500.uart", cpu_rate / 2);

	ralink_clk_add("300900.i2c", cpu_rate / 2);

	ralink_clk_add("300c00.uartlite", cpu_rate / 2);

	ralink_clk_add("400000.ethernet", cpu_rate / 2);

	ralink_clk_add("480000.wmac", wmac_rate);

}



void __init ralink_of_remap(void)

{

	rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");