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    ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ · 6ebbf2ce
    Russell King authored
    
    ARMv6 and greater introduced a new instruction ("bx") which can be used
    to return from function calls.  Recent CPUs perform better when the
    "bx lr" instruction is used rather than the "mov pc, lr" instruction,
    and this sequence is strongly recommended to be used by the ARM
    architecture manual (section A.4.1.1).
    
    We provide a new macro "ret" with all its variants for the condition
    code which will resolve to the appropriate instruction.
    
    Rather than doing this piecemeal, and miss some instances, change all
    the "mov pc" instances to use the new macro, with the exception of
    the "movs" instruction and the kprobes code.  This allows us to detect
    the "mov pc, lr" case and fix it up - and also gives us the possibility
    of deploying this for other registers depending on the CPU selection.
    
    Reported-by: default avatarWill Deacon <will.deacon@arm.com>
    Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
    Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701...
    6ebbf2ce
    History
    ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+
    Russell King authored
    
    ARMv6 and greater introduced a new instruction ("bx") which can be used
    to return from function calls.  Recent CPUs perform better when the
    "bx lr" instruction is used rather than the "mov pc, lr" instruction,
    and this sequence is strongly recommended to be used by the ARM
    architecture manual (section A.4.1.1).
    
    We provide a new macro "ret" with all its variants for the condition
    code which will resolve to the appropriate instruction.
    
    Rather than doing this piecemeal, and miss some instances, change all
    the "mov pc" instances to use the new macro, with the exception of
    the "movs" instruction and the kprobes code.  This allows us to detect
    the "mov pc, lr" case and fix it up - and also gives us the possibility
    of deploying this for other registers depending on the CPU selection.
    
    Reported-by: default avatarWill Deacon <will.deacon@arm.com>
    Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
    Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701...