Commit 042c1a5a authored by Boris Brezillon's avatar Boris Brezillon
Browse files

Merge tag 'nand/for-4.20' of git://git.infradead.org/linux-mtd into mtd/next 

NAND core changes:
- Two batchs of cleanups of the NAND API, including:
  * Deprecating a lot of interfaces (now replaced by ->exec_op()).
  * Moving code in separate drivers (JEDEC, ONFI), in private files
    (internals), in platform drivers, etc.
  * Functions/structures reordering.
  * Exclusive use of the nand_chip structure instead of the MTD one
    all across the subsystem.
- Addition of the nand_wait_readrdy/rdy_op() helpers.

Raw NAND controllers drivers changes:
- Various coccinelle patches.
- Marvell:
  * Use regmap_update_bits() for syscon access.
  * More documentation.
  * BCH failure path rework.
  * More layouts to be supported.
  * IRQ handler complete() condition fixed.
- Fsl_ifc:
  * SRAM initialization fixed for newer controller versions.
- Denali:
  * Fix licenses mismatch and use a SPDX tag.
  * Set SPARE_AREA_SKIP_BYTES register to 8 if unset.
- Qualcomm:
  * Do not include dma-direct.h.
- Docg4:
  * Removed.
- Ams-delta:
  * Use of a GPIO lookup table
  * Internal machinery changes.

Raw NAND chip drivers changes:
- Toshiba:
  * Add support for Toshiba memory BENAND
  * Pass a single nand_chip object to the status helper.
- ESMT:
  * New driver to retrieve the ECC requirements from the 5th ID byte.
parents 5cc1b66e 53c83b59

Documentation/ABI/stable/sysfs-bus-xen-backend

+9 −0
Original line number Diff line number Diff line
@@ -73,3 +73,12 @@ KernelVersion: 3.0 
Contact:	Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

Description:

                Number of sectors written by the frontend.



What:		/sys/bus/xen-backend/devices/*/state

Date:		August 2018

KernelVersion:	4.19

Contact:	Joe Jin <joe.jin@oracle.com>

Description:

                The state of the device. One of: 'Unknown',

                'Initialising', 'Initialised', 'Connected', 'Closing',

                'Closed', 'Reconfiguring', 'Reconfigured'.

Documentation/ABI/testing/sysfs-driver-xen-blkback

+10 −0
Original line number Diff line number Diff line
@@ -15,3 +15,13 @@ Description: 
                blkback. If the frontend tries to use more than

                max_persistent_grants, the LRU kicks in and starts

                removing 5% of max_persistent_grants every 100ms.



What:           /sys/module/xen_blkback/parameters/persistent_grant_unused_seconds

Date:           August 2018

KernelVersion:  4.19

Contact:        Roger Pau Monné <roger.pau@citrix.com>

Description:

                How long a persistent grant is allowed to remain

                allocated without being in use. The time is in

                seconds, 0 means indefinitely long.

                The default is 60 seconds.

Documentation/arm64/sve.txt

+2 −2
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg) 
      thread.



    * Changing the vector length causes all of P0..P15, FFR and all bits of

      Z0..V31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become

      Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become

      unspecified.  Calling PR_SVE_SET_VL with vl equal to the thread's current

      vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC

      flag, does not constitute a change to the vector length for this purpose.
@@ -500,7 +500,7 @@ References 
[2] arch/arm64/include/uapi/asm/ptrace.h

    AArch64 Linux ptrace ABI definitions



[3] linux/Documentation/arm64/cpu-feature-registers.txt

[3] Documentation/arm64/cpu-feature-registers.txt



[4] ARM IHI0055C

    http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf

Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt

+11 −3
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ The RISC-V supervisor ISA manual specifies three interrupt sources that are 
attached to every HLIC: software interrupts, the timer interrupt, and external

interrupts.  Software interrupts are used to send IPIs between cores.  The

timer interrupt comes from an architecturally mandated real-time timer that is

controller via Supervisor Binary Interface (SBI) calls and CSR reads.  External

controlled via Supervisor Binary Interface (SBI) calls and CSR reads.  External

interrupts connect all other device interrupts to the HLIC, which are routed

via the platform-level interrupt controller (PLIC).
@@ -25,7 +25,15 @@ in the system. 


Required properties:

- compatible : "riscv,cpu-intc"

- #interrupt-cells : should be <1>

- #interrupt-cells : should be <1>.  The interrupt sources are defined by the

  RISC-V supervisor ISA manual, with only the following three interrupts being

  defined for supervisor mode:

    - Source 1 is the supervisor software interrupt, which can be sent by an SBI

      call and is reserved for use by software.

    - Source 5 is the supervisor timer interrupt, which can be configured by

      SBI calls and implements a one-shot timer.

    - Source 9 is the supervisor external interrupt, which chains to all other

      device interrupts.

- interrupt-controller : Identifies the node as an interrupt controller



Furthermore, this interrupt-controller MUST be embedded inside the cpu
@@ -38,7 +46,7 @@ An example device tree entry for a HLIC is show below. 
		...

		cpu1-intc: interrupt-controller {

			#interrupt-cells = <1>;

			compatible = "riscv,cpu-intc", "sifive,fu540-c000-cpu-intc";

			compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";

			interrupt-controller;

		};

	};

Documentation/devicetree/bindings/watchdog/renesas-wdt.txt

+3 −2
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ Required properties: 
	       Examples with soctypes are:

		 - "renesas,r8a7743-wdt" (RZ/G1M)

		 - "renesas,r8a7745-wdt" (RZ/G1E)

		 - "renesas,r8a774a1-wdt" (RZ/G2M)

	         - "renesas,r8a7790-wdt" (R-Car H2)

	         - "renesas,r8a7791-wdt" (R-Car M2-W)

	         - "renesas,r8a7792-wdt" (R-Car V2H)
@@ -21,8 +22,8 @@ Required properties: 
	         - "renesas,r7s72100-wdt" (RZ/A1)

		The generic compatible string must be:

		 - "renesas,rza-wdt" for RZ/A

		 - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G

		 - "renesas,rcar-gen3-wdt" for R-Car Gen3

		 - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G1

		 - "renesas,rcar-gen3-wdt" for R-Car Gen3 and RZ/G2



- reg : Should contain WDT registers location and length

- clocks : the clock feeding the watchdog timer.