Commit 06d82d87 authored by Ran Sun's avatar Ran Sun Committed by Alex Deucher
Browse files

drm/amdgpu: Clean up errors in soc21.c 



Fix the following errors reported by checkpatch:

ERROR: that open brace { should be on the previous line

Signed-off-by: default avatarRan Sun <sunran001@208suo.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 18ef7544

drivers/gpu/drm/amd/amdgpu/soc21.c

+10 −20
Original line number Diff line number Diff line
@@ -48,33 +48,28 @@ 
static const struct amd_ip_funcs soc21_common_ip_funcs;



/* SOC21 */

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] =

{

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},

};



static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] =

{

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},

};



static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 =

{

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),

	.codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,

};



static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 =

{

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),

	.codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,

};



static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] =

{

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
@@ -82,22 +77,19 @@ static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_ 
	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},

};



static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] =

{

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},

};



static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 =

{

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),

	.codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,

};



static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 =

{

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),

	.codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,

};
@@ -445,8 +437,7 @@ static void soc21_program_aspm(struct amdgpu_device *adev) 
		adev->nbio.funcs->program_aspm(adev);

}



const struct amdgpu_ip_block_version soc21_common_ip_block =

{

const struct amdgpu_ip_block_version soc21_common_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_COMMON,

	.major = 1,

	.minor = 0,
@@ -537,8 +528,7 @@ static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 
	return 0;

}



static const struct amdgpu_asic_funcs soc21_asic_funcs =

{

static const struct amdgpu_asic_funcs soc21_asic_funcs = {

	.read_disabled_bios = &soc21_read_disabled_bios,

	.read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,

	.read_register = &soc21_read_register,