Skip to content
Commit 0925ab5d authored by Valentine Barshak's avatar Valentine Barshak Committed by Jeff Garzik
Browse files

ibm_newemac: PowerPC 440GX EMAC PHY clock workaround



The PowerPC 440GX Taishan board fails to reset EMAC3 (reset timeout
error) if there's no link. Because of that it fails to find PHY
chip. The older ibm_emac driver had a workaround for that: the
EMAC_CLK_INTERNAL/EMAC_CLK_EXTERNAL macros, which toggle the Ethernet
Clock Select bit in the SDR0_MFR register. This patch does the same for
"ibm,emac-440gx" compatible chips. The workaround forces clock on -all-
EMACs, so we select clock under global emac_phy_map_lock.

BenH: Made that #ifdef CONFIG_PPC_DCR_NATIVE for now as dcri_* stuff
doesn't exist for MMIO type DCRs like Cell. Some future rework &
improvements of the DCR infrastructure will make that cleaner but
for now, this makes it work.

Signed-off-by: default avatarValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarJeff Garzik <jgarzik@redhat.com>
parent be63c09a
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment