Commit 0bb5675b authored May 08, 2022 by Jonathan Cameron

iio: frequency: adf4371: Fix alignment for DMA safety



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: 7f699bd1 ("iio: frequency: adf4371: Add support for ADF4371 PLL")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-68-jic23@kernel.org

parent 389b8972

drivers/iio/frequency/adf4371.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -175,7 +175,7 @@ struct adf4371_state {
	unsigned int mod2;		unsigned int mod2;
	unsigned int rf_div_sel;		unsigned int rf_div_sel;
	unsigned int ref_div_factor;		unsigned int ref_div_factor;
	u8 buf[10] ____cacheline_aligned;		u8 buf[10] __aligned(IIO_DMA_MINALIGN);
	};		};

	static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st,		static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st,