Commit 389b8972 authored by Jonathan Cameron's avatar Jonathan Cameron
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iio: frequency: adf4350: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Updated help text to 'may' require buffers to be in their own cacheline.

Fixes: e31166f0 ("iio: frequency: New driver for Analog Devices ADF4350/ADF4351 Wideband Synthesizers")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-67-jic23@kernel.org
parent 8ff2eb62

drivers/iio/frequency/adf4350.c

+3 −3
Original line number Diff line number Diff line
@@ -56,10 +56,10 @@ struct adf4350_state { 
	 */

	struct mutex			lock;

	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * transfer buffers to live in their own cache lines.

	 * DMA (thus cache coherency maintenance) may require that

	 * transfer buffers live in their own cache lines.

	 */

	__be32				val ____cacheline_aligned;

	__be32				val __aligned(IIO_DMA_MINALIGN);

};



static struct adf4350_platform_data default_pdata = {