Commit 115efa44 authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu/gfx10: use INVALIDATE_TLBS to invalidate TLBs v2 



For MES queue VM flush, use INVALIDATE_TLBS to invalidate TLBs.
This packet can let CP firmware to determine the current vmid
and inv eng to invalidate.

v2: unify invalidate_tlbs functions

Cc: Le Ma <le.ma@amd.com>
Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1f0f303c

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+20 −7
Original line number Diff line number Diff line
@@ -3503,6 +3503,9 @@ static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 
static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);

static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);

static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);

static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,

					   uint16_t pasid, uint32_t flush_type,

					   bool all_hub, uint8_t dst_sel);



static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)

{
@@ -3595,12 +3598,7 @@ static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 
				uint16_t pasid, uint32_t flush_type,

				bool all_hub)

{

	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));

	amdgpu_ring_write(kiq_ring,

			PACKET3_INVALIDATE_TLBS_DST_SEL(1) |

			PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |

			PACKET3_INVALIDATE_TLBS_PASID(pasid) |

			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));

	gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);

}



static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
@@ -8700,9 +8698,24 @@ static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 
			       upper_32_bits(addr), seq, 0xffffffff, 4);

}



static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,

				   uint16_t pasid, uint32_t flush_type,

				   bool all_hub, uint8_t dst_sel)

{

	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));

	amdgpu_ring_write(ring,

			  PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |

			  PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |

			  PACKET3_INVALIDATE_TLBS_PASID(pasid) |

			  PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));

}



static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,

					 unsigned vmid, uint64_t pd_addr)

{

	if (ring->is_mes_queue)

		gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);

	else

		amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);



	/* compute doesn't have PFP */