Commit 1f0f303c authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu/gfx10: inherit vmid from mqd 



For MES manages vmid assignment, let vmid inherit from mqd instead of
ib packet setting.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 11f39576

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+8 −0
Original line number Diff line number Diff line
@@ -8602,6 +8602,10 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 
				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);

	}



	if (ring->is_mes_queue)

		/* inherit vmid from mqd */

		control |= 0x400000;



	amdgpu_ring_write(ring, header);

	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */

	amdgpu_ring_write(ring,
@@ -8621,6 +8625,10 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 
	unsigned vmid = AMDGPU_JOB_GET_VMID(job);

	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);



	if (ring->is_mes_queue)

		/* inherit vmid from mqd */

		control |= 0x40000000;



	/* Currently, there is a high possibility to get wave ID mismatch

	 * between ME and GDS, leading to a hw deadlock, because ME generates

	 * different wave IDs than the GDS expects. This situation happens