Commit 11f39576 authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
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drm/amdgpu/gfx10: associate mes queue id with fence v2 



Associate mes queue id with fence, so that EOP trap handler can look up
which queue has issued the fence.

v2: move mes queue flag to amdgpu_mes_ctx.h

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 34ec3c2e

drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

+2 −0
Original line number Diff line number Diff line
@@ -115,4 +115,6 @@ struct amdgpu_mes_ctx_data { 
#define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u

#define AMDGPU_FENCE_MES_QUEUE_ID_MASK  (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)



#define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u



#endif

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+2 −1
Original line number Diff line number Diff line
@@ -8678,7 +8678,8 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 
	amdgpu_ring_write(ring, upper_32_bits(addr));

	amdgpu_ring_write(ring, lower_32_bits(seq));

	amdgpu_ring_write(ring, upper_32_bits(seq));

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, ring->is_mes_queue ?

			 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);

}



static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)