Commit 34ec3c2e authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
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drm/amdgpu/gfx10: use per ctx CSA for de metadata 



As MES requires per context preemption, use per context CSA address
for DE metadata to correctly enable context MCBP preemption.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 75df9e88

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+28 −11
Original line number Original line Diff line number Diff line
@@ -8889,12 +8889,33 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 
{

{

	struct amdgpu_device *adev = ring->adev;

	struct amdgpu_device *adev = ring->adev;

	struct v10_de_ib_state de_payload = {0};

	struct v10_de_ib_state de_payload = {0};

	uint64_t csa_addr, gds_addr;

	uint64_t offset, gds_addr, de_payload_gpu_addr;

	void *de_payload_cpu_addr;

	int cnt;

	int cnt;





	csa_addr = amdgpu_csa_vaddr(ring->adev);

	if (ring->is_mes_queue) {

	gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,

		offset = offsetof(struct amdgpu_mes_ctx_meta_data,

				  gfx[0].gfx_meta_data) +

			offsetof(struct v10_gfx_meta_data, de_payload);

		de_payload_gpu_addr =

			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);

		de_payload_cpu_addr =

			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);



		offset = offsetof(struct amdgpu_mes_ctx_meta_data,

				  gfx[0].gds_backup) +

			offsetof(struct v10_gfx_meta_data, de_payload);

		gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);

	} else {

		offset = offsetof(struct v10_gfx_meta_data, de_payload);

		de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;

		de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;



		gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +

				 AMDGPU_CSA_SIZE - adev->gds.gds_size,

				 PAGE_SIZE);

				 PAGE_SIZE);

	}



	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);

	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);

	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);

	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
@@ -8904,15 +8925,11 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 
				 WRITE_DATA_DST_SEL(8) |

				 WRITE_DATA_DST_SEL(8) |

				 WR_CONFIRM) |

				 WR_CONFIRM) |

				 WRITE_DATA_CACHE_POLICY(0));

				 WRITE_DATA_CACHE_POLICY(0));

	amdgpu_ring_write(ring, lower_32_bits(csa_addr +

	amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));

			      offsetof(struct v10_gfx_meta_data, de_payload)));

	amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));

	amdgpu_ring_write(ring, upper_32_bits(csa_addr +

			      offsetof(struct v10_gfx_meta_data, de_payload)));





	if (resume)

	if (resume)

		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +

		amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,

					   offsetof(struct v10_gfx_meta_data,

						    de_payload),

					   sizeof(de_payload) >> 2);

					   sizeof(de_payload) >> 2);

	else

	else

		amdgpu_ring_write_multiple(ring, (void *)&de_payload,

		amdgpu_ring_write_multiple(ring, (void *)&de_payload,