Commit 135ad96c authored by Benjamin Gaignard's avatar Benjamin Gaignard Committed by Mauro Carvalho Chehab
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media: hantro: Be more accurate on pixel formats step_width constraints 



On Hantro G2 decoder on IMX8MQ strides requirements aren't the same
for NV12_4L4 and NV12 pixel formats. The first one use a 4 bytes padding
while the last one needs 16 bytes.
To be sure to provide the correct stride in all cases we need:
- to relax the constraints on codec formats so set step_width to 4
- use capture queue format and not the output queue format when applying
  the pixel format constraints.
- put the correct step_width constraints on each pixel format.

Move HEVC SPS validation in hantro_hevc.c to be able to perform it
when setting sps control and when starting to decode the bitstream.
Add a new test in HEVC SPS validation function to check if resolution
is still matching the hardware constraints.

With this SAODBLK_A_MainConcept_4 and SAODBLK_B_MainConcept_4 conformance
tests files are correctly decoded with both NV12 and NV12_4L4 pixel
formats. These two files have a resolution of 1016x760.

Add defines for the various used resolutions.
For other variants than Hantro G2 on IMX8M keep the same step_width to
avoid regressions.

Fluster HEVC test score is now 128/147 vs 126/147 with the both pixel
formats as decoder output.
Fluster VP9 test score stay at 147/303.

[hverkuil: fix trivial checkpatch warnings]

Signed-off-by: default avatarBenjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parent ca9dc8d0

drivers/staging/media/hantro/hantro_drv.c

+6 −6
Original line number Diff line number Diff line
@@ -253,6 +253,11 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) 


static int hantro_try_ctrl(struct v4l2_ctrl *ctrl)

{

	struct hantro_ctx *ctx;



	ctx = container_of(ctrl->handler,

			   struct hantro_ctx, ctrl_handler);



	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {

		const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
@@ -268,12 +273,7 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) 
	} else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) {

		const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;



		if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)

			/* Luma and chroma bit depth mismatch */

			return -EINVAL;

		if (sps->bit_depth_luma_minus8 != 0)

			/* Only 8-bit is supported */

			return -EINVAL;

		return hantro_hevc_validate_sps(ctx, sps);

	} else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) {

		const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame;

drivers/staging/media/hantro/hantro_hevc.c

+30 −0
Original line number Diff line number Diff line
@@ -154,6 +154,32 @@ static int tile_buffer_reallocate(struct hantro_ctx *ctx) 
	return -ENOMEM;

}



int hantro_hevc_validate_sps(struct hantro_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps)

{

	if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)

		/* Luma and chroma bit depth mismatch */

		return -EINVAL;

	if (sps->bit_depth_luma_minus8 != 0)

		/* Only 8-bit is supported */

		return -EINVAL;



	/*

	 * for tile pixel format check if the width and height match

	 * hardware constraints

	 */

	if (ctx->vpu_dst_fmt->fourcc == V4L2_PIX_FMT_NV12_4L4) {

		if (ctx->dst_fmt.width !=

		    ALIGN(sps->pic_width_in_luma_samples, ctx->vpu_dst_fmt->frmsize.step_width))

			return -EINVAL;



		if (ctx->dst_fmt.height !=

		    ALIGN(sps->pic_height_in_luma_samples, ctx->vpu_dst_fmt->frmsize.step_height))

			return -EINVAL;

	}



	return 0;

}



int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx)

{

	struct hantro_hevc_dec_hw_ctx *hevc_ctx = &ctx->hevc_dec;
@@ -177,6 +203,10 @@ int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx) 
	if (WARN_ON(!ctrls->sps))

		return -EINVAL;



	ret = hantro_hevc_validate_sps(ctx, ctrls->sps);

	if (ret)

		return ret;



	ctrls->pps =

		hantro_get_ctrl(ctx, V4L2_CID_MPEG_VIDEO_HEVC_PPS);

	if (WARN_ON(!ctrls->pps))

drivers/staging/media/hantro/hantro_hw.h

+14 −0
Original line number Diff line number Diff line
@@ -18,9 +18,21 @@ 
#define DEC_8190_ALIGN_MASK	0x07U



#define MB_DIM			16

#define TILE_MB_DIM		4

#define MB_WIDTH(w)		DIV_ROUND_UP(w, MB_DIM)

#define MB_HEIGHT(h)		DIV_ROUND_UP(h, MB_DIM)



#define FMT_MIN_WIDTH		48

#define FMT_MIN_HEIGHT		48

#define FMT_HD_WIDTH		1280

#define FMT_HD_HEIGHT		720

#define FMT_FHD_WIDTH		1920

#define FMT_FHD_HEIGHT		1088

#define FMT_UHD_WIDTH		3840

#define FMT_UHD_HEIGHT		2160

#define FMT_4K_WIDTH		4096

#define FMT_4K_HEIGHT		2304



#define NUM_REF_PICTURES	(V4L2_HEVC_DPB_ENTRIES_NUM_MAX + 1)



struct hantro_dev;
@@ -347,6 +359,8 @@ int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx); 
void hantro_hevc_ref_init(struct hantro_ctx *ctx);

dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, int poc);

int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr);

int hantro_hevc_validate_sps(struct hantro_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps);





static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension)

{

drivers/staging/media/hantro/hantro_v4l2.c

+1 −1
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx, 
	} else if (ctx->is_encoder) {

		vpu_fmt = ctx->vpu_dst_fmt;

	} else {

		vpu_fmt = ctx->vpu_src_fmt;

		vpu_fmt = fmt;

		/*

		 * Width/height on the CAPTURE end of a decoder are ignored and

		 * replaced by the OUTPUT ones.

drivers/staging/media/hantro/imx8m_vpu_hw.c

+56 −24
Original line number Diff line number Diff line
@@ -83,6 +83,14 @@ static const struct hantro_fmt imx8m_vpu_postproc_fmts[] = { 
		.fourcc = V4L2_PIX_FMT_YUYV,

		.codec_mode = HANTRO_MODE_NONE,

		.postprocessed = true,

		.frmsize = {

			.min_width = FMT_MIN_WIDTH,

			.max_width = FMT_UHD_WIDTH,

			.step_width = MB_DIM,

			.min_height = FMT_MIN_HEIGHT,

			.max_height = FMT_UHD_HEIGHT,

			.step_height = MB_DIM,

		},

	},

};
@@ -90,17 +98,25 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { 
	{

		.fourcc = V4L2_PIX_FMT_NV12,

		.codec_mode = HANTRO_MODE_NONE,

		.frmsize = {

			.min_width = FMT_MIN_WIDTH,

			.max_width = FMT_UHD_WIDTH,

			.step_width = MB_DIM,

			.min_height = FMT_MIN_HEIGHT,

			.max_height = FMT_UHD_HEIGHT,

			.step_height = MB_DIM,

		},

	},

	{

		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,

		.codec_mode = HANTRO_MODE_MPEG2_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 1920,

			.min_width = FMT_MIN_WIDTH,

			.max_width = FMT_FHD_WIDTH,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 1088,

			.min_height = FMT_MIN_HEIGHT,

			.max_height = FMT_FHD_HEIGHT,

			.step_height = MB_DIM,

		},

	},
@@ -109,11 +125,11 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { 
		.codec_mode = HANTRO_MODE_VP8_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 3840,

			.min_width = FMT_MIN_WIDTH,

			.max_width = FMT_UHD_WIDTH,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 2160,

			.min_height = FMT_MIN_HEIGHT,

			.max_height = FMT_UHD_HEIGHT,

			.step_height = MB_DIM,

		},

	},
@@ -122,11 +138,11 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { 
		.codec_mode = HANTRO_MODE_H264_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 3840,

			.min_width = FMT_MIN_WIDTH,

			.max_width = FMT_UHD_WIDTH,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 2160,

			.min_height = FMT_MIN_HEIGHT,

			.max_height = FMT_UHD_HEIGHT,

			.step_height = MB_DIM,

		},

	},
@@ -137,6 +153,14 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { 
		.fourcc = V4L2_PIX_FMT_NV12,

		.codec_mode = HANTRO_MODE_NONE,

		.postprocessed = true,

		.frmsize = {

			.min_width = FMT_MIN_WIDTH,

			.max_width = FMT_UHD_WIDTH,

			.step_width = MB_DIM,

			.min_height = FMT_MIN_HEIGHT,

			.max_height = FMT_UHD_HEIGHT,

			.step_height = MB_DIM,

		},

	},

};
@@ -144,18 +168,26 @@ static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { 
	{

		.fourcc = V4L2_PIX_FMT_NV12_4L4,

		.codec_mode = HANTRO_MODE_NONE,

		.frmsize = {

			.min_width = FMT_MIN_WIDTH,

			.max_width = FMT_UHD_WIDTH,

			.step_width = TILE_MB_DIM,

			.min_height = FMT_MIN_HEIGHT,

			.max_height = FMT_UHD_HEIGHT,

			.step_height = TILE_MB_DIM,

		},

	},

	{

		.fourcc = V4L2_PIX_FMT_HEVC_SLICE,

		.codec_mode = HANTRO_MODE_HEVC_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 3840,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 2160,

			.step_height = MB_DIM,

			.min_width = FMT_MIN_WIDTH,

			.max_width = FMT_UHD_WIDTH,

			.step_width = TILE_MB_DIM,

			.min_height = FMT_MIN_HEIGHT,

			.max_height = FMT_UHD_HEIGHT,

			.step_height = TILE_MB_DIM,

		},

	},

	{
@@ -163,12 +195,12 @@ static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { 
		.codec_mode = HANTRO_MODE_VP9_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 3840,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 2160,

			.step_height = MB_DIM,

			.min_width = FMT_MIN_WIDTH,

			.max_width = FMT_UHD_WIDTH,

			.step_width = TILE_MB_DIM,

			.min_height = FMT_MIN_HEIGHT,

			.max_height = FMT_UHD_HEIGHT,

			.step_height = TILE_MB_DIM,

		},

	},

};