Commit 1650ac53 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Introduce a host helper function to share re-tuning progress

  MMC host:
   - sdhci: Add support for v4 host mode
   - sdhci-of-arasan: Add Support for AM654 MMC and PHY
   - sdhci-sprd: Add support for Spreadtrum's host controller
   - sdhci-tegra: Add support for HS400 enhanced strobe
   - sdhci-tegra: Enable UHS/HS200 modes for Tegra186/210
   - sdhci-tegra: Add support for HS400 delay line calibration
   - sdhci-tegra: Add support for pad calibration
   - sdhci-of-dwcmshc: Address 128MB DMA boundary limitation
   - sdhci-of-esdhc: Add support for tuning erratum A008171
   - sdhci-iproc: Add ACPI support
   - mediatek: Add support for MT8183
   - mediatek: Improve the support for tuning
   - mediatek: Add bus clock control for MT2712
   - jz4740: Add support for the JZ4725B
   - mmci: Add support for the stm32 sdmmc variant
   - mmci: Add support for an optional reset control
   - mmci: Add some new variant specific properties/callbacks
   - mmci: Re-structure DMA code to prepare for new variants
   - renesas_sdhi: Add support for r8a77470, r8a7744 and r8a774a1
   - renesas_sdhi_internal_dmac: Whitelist r8a77970 and r8a774a1
   - tmio/uniphier-sd: Add new UniPhier SD/eMMC controller driver
   - tmio/renesas_sdhi: Deal properly with SCC detection during re-tune
   - tmio/renesas_sdhi: Refactor/consolidate clock management
   - omap_hsmmc: Drop cover detection and some unused platform data
   - dw_mmc-exynos: Enable tuning for more speed modes
   - sunxi: Clarify the new timing mode and enable it for the A64 controller
   - various: Convert to slot GPIO descriptors"

* tag 'mmc-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (129 commits)
  mmc: mediatek: drop too much code of tuning method
  mmc: mediatek: add MT8183 MMC driver support
  mmc: mediatek: tune CMD/DATA together
  mmc: mediatek: fix cannot receive new request when msdc_cmd_is_ready fail
  mmc: mediatek: fill the actual clock for mmc debugfs
  mmc: dt-bindings: add support for MT8183 SoC
  mmc: uniphier-sd: avoid using broken DMA RX channel
  mmc: uniphier-sd: fix DMA disabling
  mmc: tmio: simplify the DMA mode test
  mmc: tmio: remove TMIO_MMC_HAVE_HIGH_REG flag
  mmc: tmio: move MFD variant reset to a platform hook
  mmc: renesas_sdhi: Add r8a77470 SDHI1 support
  dt-bindings: mmc: renesas_sdhi: Add r8a77470 support
  mmc: mmci: add stm32 sdmmc variant
  dt-bindings: mmci: add stm32 sdmmc variant
  mmc: mmci: add stm32 sdmmc registers
  mmc: mmci: add clock divider for stm32 sdmmc
  mmc: mmci: add optional reset property
  dt-bindings: mmci: add optional reset property
  mmc: mmci: add variant property to not read datacnt
  ...
parents ca9eb48f fd82cc30

Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Required Properties: 
    - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY

    - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY

      For this device it is strongly suggested to include arasan,soc-ctl-syscon.

    - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY

  - reg: From mmc bindings: Register location and length.

  - clocks: From clock bindings: Handles to clock inputs.

  - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"

Documentation/devicetree/bindings/mmc/jz4740.txt

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ described in mmc.txt. 
Required properties:

- compatible: Should be one of the following:

  - "ingenic,jz4740-mmc" for the JZ4740

  - "ingenic,jz4725b-mmc" for the JZ4725B

  - "ingenic,jz4780-mmc" for the JZ4780

- reg: Should contain the MMC controller registers location and length.

- interrupts: Should contain the interrupt specifier of the MMC controller.

Documentation/devicetree/bindings/mmc/mmci.txt

+11 −0
Original line number Diff line number Diff line
@@ -15,8 +15,11 @@ Required properties: 
Optional properties:

- arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides

                           the ID provided by the HW

- resets                 : phandle to internal reset line.

			   Should be defined for sdmmc variant.

- vqmmc-supply           : phandle to the regulator device tree node, mentioned

                           as the VCCQ/VDD_IO supply in the eMMC/SD specs.

specific for ux500 variant:

- st,sig-dir-dat0        : bus signal direction pin used for DAT[0].

- st,sig-dir-dat2        : bus signal direction pin used for DAT[2].

- st,sig-dir-dat31       : bus signal direction pin used for DAT[3] and DAT[1].
@@ -24,6 +27,14 @@ Optional properties: 
- st,sig-dir-cmd         : cmd signal direction pin used for CMD.

- st,sig-pin-fbclk       : feedback clock signal pin used.



specific for sdmmc variant:

- st,sig-dir             : signal direction polarity used for cmd, dat0 dat123.

- st,neg-edge            : data & command phase relation, generated on

                           sd clock falling edge.

- st,use-ckin            : use ckin pin from an external driver to sample

                           the receive data (example: with voltage

			   switch transceiver).



Deprecated properties:

- mmc-cap-mmc-highspeed  : indicates whether MMC is high speed capable.

- mmc-cap-sd-highspeed   : indicates whether SD is high speed capable.

Documentation/devicetree/bindings/mmc/mtk-sd.txt

+2 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Required properties: 
- compatible: value should be either of the following.

	"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135

	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173

	"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183

	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701

	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712

	"mediatek,mt7622-mmc": for MT7622 SoC
@@ -22,6 +23,7 @@ Required properties: 
	"source" - source clock (required)

	"hclk" - HCLK which used for host (required)

	"source_cg" - independent source clock gate (required for MT2712)

	"bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)

- pinctrl-names: should be "default", "state_uhs"

- pinctrl-0: should contain default/high speed pin ctrl

- pinctrl-1: should contain uhs mode pin ctrl

Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt

+72 −0
Original line number Diff line number Diff line
@@ -38,3 +38,75 @@ sdhci@c8000200 { 
	power-gpios = <&gpio 155 0>; /* gpio PT3 */

	bus-width = <8>;

};



Optional properties for Tegra210 and Tegra186:

- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage

  configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"

  for controllers supporting multiple voltage levels. The order of names

  should correspond to the pin configuration states in pinctrl-0 and

  pinctrl-1.

- nvidia,only-1-8-v : The presence of this property indicates that the

  controller operates at a 1.8 V fixed I/O voltage.

- nvidia,pad-autocal-pull-up-offset-3v3,

  nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength

  calibration offsets for 3.3 V signaling modes.

- nvidia,pad-autocal-pull-up-offset-1v8,

  nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength

  calibration offsets for 1.8 V signaling modes.

- nvidia,pad-autocal-pull-up-offset-3v3-timeout,

  nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive

  strength used as a fallback in case the automatic calibration times

  out on a 3.3 V signaling mode.

- nvidia,pad-autocal-pull-up-offset-1v8-timeout,

  nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive

  strength used as a fallback in case the automatic calibration times

  out on a 1.8 V signaling mode.

- nvidia,pad-autocal-pull-up-offset-sdr104,

  nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength

  calibration offsets for SDR104 mode.

- nvidia,pad-autocal-pull-up-offset-hs400,

  nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength

  calibration offsets for HS400 mode.

- nvidia,default-tap : Specify the default inbound sampling clock

  trimmer value for non-tunable modes.

- nvidia,default-trim : Specify the default outbound clock trimmer

  value.

- nvidia,dqs-trim : Specify DQS trim value for HS400 timing



  Notes on the pad calibration pull up and pulldown offset values:

    - The property values are drive codes which are programmed into the

      PD_OFFSET and PU_OFFSET sections of the

      SDHCI_TEGRA_AUTO_CAL_CONFIG register.

    - A higher value corresponds to higher drive strength. Please refer

      to the reference manual of the SoC for correct values.

    - The SDR104 and HS400 timing specific values are used in

      corresponding modes if specified.



  Notes on tap and trim values:

    - The values are used for compensating trace length differences

      by adjusting the sampling point.

    - The values are programmed to the Vendor Clock Control Register.

      Please refer to the reference manual of the SoC for correct

      values.

    - The DQS trim values are only used on controllers which support

      HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports

      HS400.



Example:

sdhci@700b0000 {

	compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";

	reg = <0x0 0x700b0000 0x0 0x200>;

	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;

	clock-names = "sdhci";

	resets = <&tegra_car 14>;

	reset-names = "sdhci";

	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";

	pinctrl-0 = <&sdmmc1_3v3>;

	pinctrl-1 = <&sdmmc1_1v8>;

	nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;

	nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;

	nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;

	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;

	status = "disabled";

};