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Commit 1790b649 authored by Eric Huang's avatar Eric Huang Committed by Alex Deucher
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drm/amdkfd: enable heavy-weight TLB flush on Vega20 



It is to meet the requirement for memory allocation
optimization on MI50.

Signed-off-by: default avatarEric Huang <jinhuieric.huang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 039cacd2
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