Commit 1c70d3d9 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/nbio: switch to amdgpu_nbio_ras_late_init helper function 



amdgpu_nbio_ras_late_init is used to init nbio specfic
ras debugfs/sysfs node and nbio specific interrupt handler.
It can be shared among nbio generations

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 47930de4

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -54,7 +54,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ 
	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \

	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \

	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \

	amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o

	amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \

	smu_v11_0_i2c.o



amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o

drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c

0 → 100644
+70 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2019  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */



#include "amdgpu.h"

#include "amdgpu_ras.h"



int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)

{

	int r;

	struct ras_ih_if ih_info = {

		.cb = NULL,

	};

	struct ras_fs_if fs_info = {

		.sysfs_name = "pcie_bif_err_count",

		.debugfs_name = "pcie_bif_err_inject",

	};



	if (!adev->nbio.ras_if) {

		adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);

		if (!adev->nbio.ras_if)

			return -ENOMEM;

		adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;

		adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;

		adev->nbio.ras_if->sub_block_index = 0;

		strcpy(adev->nbio.ras_if->name, "pcie_bif");

	}

	ih_info.head = fs_info.head = *adev->nbio.ras_if;

	r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,

				 &fs_info, &ih_info);

	if (r)

		goto free;



	if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {

		r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);

		if (r)

			goto late_fini;

		r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);

		if (r)

			goto late_fini;

	} else {

		r = 0;

		goto free;

	}



	return 0;

late_fini:

	amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);

free:

	kfree(adev->nbio.ras_if);

	adev->nbio.ras_if = NULL;

	return r;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h

+2 −0
Original line number Diff line number Diff line
@@ -92,4 +92,6 @@ struct amdgpu_nbio { 
	const struct amdgpu_nbio_funcs *funcs;

};



int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev);



#endif

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

+1 −48
Original line number Diff line number Diff line
@@ -474,53 +474,6 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a 
	return 0;

}



static int nbio_v7_4_ras_late_init(struct amdgpu_device *adev)

{

	int r;

	struct ras_ih_if ih_info = {

		.cb = NULL,

	};

	struct ras_fs_if fs_info = {

		.sysfs_name = "pcie_bif_err_count",

		.debugfs_name = "pcie_bif_err_inject",

	};



	if (!adev->nbio.ras_if) {

		adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);

		if (!adev->nbio.ras_if)

			return -ENOMEM;

		adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;

		adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;

		adev->nbio.ras_if->sub_block_index = 0;

		strcpy(adev->nbio.ras_if->name, "pcie_bif");

	}

	ih_info.head = fs_info.head = *adev->nbio.ras_if;

	r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,

				 &fs_info, &ih_info);

	if (r)

		goto free;



	if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {

		r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);

		if (r)

			goto late_fini;

		r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);

		if (r)

			goto late_fini;

	} else {

		r = 0;

		goto free;

	}



	return 0;

late_fini:

	amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);

free:

	kfree(adev->nbio.ras_if);

	adev->nbio.ras_if = NULL;

	return r;

}



const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {

	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,

	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
@@ -546,5 +499,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 
	.handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,

	.init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,

	.init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,

	.ras_late_init = nbio_v7_4_ras_late_init,

	.ras_late_init = amdgpu_nbio_ras_late_init,

};