Commit 1e74c05b authored by Yihan Zhu's avatar Yihan Zhu Committed by Alex Deucher
Browse files

drm/amd/display: update pixel format in DP hw sequence 



[WHY]
DP 420 formats do not light up because the pixel processing mode
of the DP_FORMAT is misprogrammed

[HOW]
Added appropriate programming for DP pixel format

Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarYihan Zhu <yihan.zhu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9bb10b7a

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c

+6 −0
Original line number Diff line number Diff line
@@ -296,12 +296,14 @@ static void enc314_stream_encoder_dp_unblank( 
		uint32_t n_vid = 0x8000;

		uint32_t m_vid;

		uint32_t n_multiply = 0;

		uint32_t pix_per_cycle = 0;

		uint64_t m_vid_l = n_vid;



		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */

		if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) {

			/*this logic should be the same in get_pixel_clock_parameters() */

			n_multiply = 1;

			pix_per_cycle = 1;

		}

		/* M / N = Fstream / Flink

		 * m_vid / n_vid = pixel rate / link rate
@@ -329,6 +331,10 @@ static void enc314_stream_encoder_dp_unblank( 
		REG_UPDATE_2(DP_VID_TIMING,

				DP_VID_M_N_GEN_EN, 1,

				DP_VID_N_MUL, n_multiply);



		REG_UPDATE(DP_PIXEL_FORMAT,

				DP_PIXEL_PER_CYCLE_PROCESSING_MODE,

				pix_per_cycle);

	}



	/* make sure stream is disabled before resetting steer fifo */