Commit 22616eb5 authored by Dennis Li's avatar Dennis Li Committed by Alex Deucher
Browse files

drm/amdgpu: add ras support for gfx of aldebaran 



add edc counter/status reset and query functions for gfx block of
aldebaran.

v2: change to clear edc counter explicitly
aldebaran hardware will not clear edc counter after driver reading them,
so driver should clear them explicitly.

Signed-off-by: default avatarDennis Li <Dennis.Li@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5217811e

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include "clearstate_defs.h"

#include "amdgpu_ring.h"

#include "amdgpu_rlc.h"

#include "soc15.h"



/* GFX current status */

#define AMDGPU_GFX_NORMAL_MODE			0x00000000L

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+14 −0
Original line number Diff line number Diff line
@@ -2113,6 +2113,19 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = { 
	.query_ras_error_status = &gfx_v9_4_query_ras_error_status,

};



static const struct amdgpu_gfx_funcs gfx_v9_4_2_gfx_funcs = {

	.get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,

	.select_se_sh = &gfx_v9_0_select_se_sh,

	.read_wave_data = &gfx_v9_0_read_wave_data,

	.read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,

	.read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,

	.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,

	.ras_error_inject = &gfx_v9_4_2_ras_error_inject,

	.query_ras_error_count = &gfx_v9_4_2_query_ras_error_count,

	.reset_ras_error_count = &gfx_v9_4_2_reset_ras_error_count,

	.query_ras_error_status = &gfx_v9_4_2_query_ras_error_status,

};



static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)

{

	u32 gb_addr_config;
@@ -2185,6 +2198,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 
		gb_addr_config |= 0x22010042;

		break;

	case CHIP_ALDEBARAN:

		adev->gfx.funcs = &gfx_v9_4_2_gfx_funcs;

		adev->gfx.config.max_hw_contexts = 8;

		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

+1078 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h

+6 −0
Original line number Diff line number Diff line
@@ -29,4 +29,10 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, 
void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,

				      uint32_t die_id);

void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev);



void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev);

int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if);

void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev);

int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,

				   void *ras_error_status);

#endif /* __GFX_V9_4_2_H__ */

drivers/gpu/drm/amd/amdgpu/soc15.h

+11 −0
Original line number Diff line number Diff line
@@ -49,6 +49,13 @@ struct soc15_reg_rlcg { 
	u32	reg;

};



struct soc15_reg {

	uint32_t hwip;

	uint32_t inst;

	uint32_t seg;

	uint32_t reg_offset;

};



struct soc15_reg_entry {

	uint32_t hwip;

	uint32_t inst;
@@ -88,6 +95,10 @@ struct soc15_ras_field_entry { 


#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT



#define SOC15_REG_FIELD_VAL(val, mask, shift)	(((val) & mask) >> shift)



#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL(val, entry.field##_count_mask, entry.field##_count_shift)



void soc15_grbm_select(struct amdgpu_device *adev,

		    u32 me, u32 pipe, u32 queue, u32 vmid);

void soc15_set_virt_ops(struct amdgpu_device *adev);