Commit 25940788 authored by Sankeerth Billakanti's avatar Sankeerth Billakanti Committed by Bjorn Andersson
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arm64: dts: qcom: sc7280: add edp display dt nodes 



Add edp controller and phy DT nodes for sc7280.

Signed-off-by: default avatarSankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: default avatarKrishna Manikandan <quic_mkrishn@quicinc.com>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1640361793-26486-4-git-send-email-quic_sbillaka@quicinc.com
parent 43137272

arch/arm64/boot/dts/qcom/sc7280.dtsi

+105 −2
Original line number Diff line number Diff line
@@ -2770,8 +2770,8 @@ dispcc: clock-controller@af00000 { 
				 <&mdss_dsi_phy 1>,

				 <0>,

				 <0>,

				 <0>,

				 <0>;

				 <&mdss_edp_phy 0>,

				 <&mdss_edp_phy 1>;

			clock-names = "bi_tcxo",

				      "gcc_disp_gpll0_clk",

				      "dsi0_phy_pll_out_byteclk",
@@ -2859,6 +2859,13 @@ dpu_intf1_out: endpoint { 
							remote-endpoint = <&dsi0_in>;

						};

					};



					port@1 {

						reg = <1>;

						dpu_intf5_out: endpoint {

							remote-endpoint = <&edp_in>;

						};

					};

				};



				mdp_opp_table: opp-table {
@@ -2974,6 +2981,102 @@ mdss_dsi_phy: phy@ae94400 { 


				status = "disabled";

			};



			mdss_edp: edp@aea0000 {

				compatible = "qcom,sc7280-edp";



				reg = <0 0xaea0000 0 0x200>,

				      <0 0xaea0200 0 0x200>,

				      <0 0xaea0400 0 0xc00>,

				      <0 0xaea1000 0 0x400>;



				interrupt-parent = <&mdss>;

				interrupts = <14>;



				clocks = <&rpmhcc RPMH_CXO_CLK>,

					 <&gcc GCC_EDP_CLKREF_EN>,

					 <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,

					 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,

					 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;

				clock-names = "core_xo",

					      "core_ref",

					      "core_iface",

					      "core_aux",

					      "ctrl_link",

					      "ctrl_link_iface",

					      "stream_pixel";

				#clock-cells = <1>;

				assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,

						  <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;

				assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;



				phys = <&mdss_edp_phy>;

				phy-names = "dp";



				operating-points-v2 = <&edp_opp_table>;

				power-domains = <&rpmhpd SC7280_CX>;



				#address-cells = <1>;

				#size-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;

					port@0 {

						reg = <0>;

						edp_in: endpoint {

							remote-endpoint = <&dpu_intf5_out>;

						};

					};

				};



				edp_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-160000000 {

						opp-hz = /bits/ 64 <160000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-270000000 {

						opp-hz = /bits/ 64 <270000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-540000000 {

						opp-hz = /bits/ 64 <540000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};



					opp-810000000 {

						opp-hz = /bits/ 64 <810000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};

				};

			};



			mdss_edp_phy: phy@aec2a00 {

				compatible = "qcom,sc7280-edp-phy";



				reg = <0 0xaec2a00 0 0x19c>,

				      <0 0xaec2200 0 0xa0>,

				      <0 0xaec2600 0 0xa0>,

				      <0 0xaec2000 0 0x1c0>;



				clocks = <&rpmhcc RPMH_CXO_CLK>,

					 <&gcc GCC_EDP_CLKREF_EN>;

				clock-names = "aux",

					      "cfg_ahb";



				#clock-cells = <1>;

				#phy-cells = <0>;



				status = "disabled";

			};

		};



		pdc: interrupt-controller@b220000 {