Commit 43137272 authored by Rajeev Nandan's avatar Rajeev Nandan Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sc7280: Add DSI display nodes 



Add DSI controller and PHY nodes for sc7280.

Signed-off-by: default avatarRajeev Nandan <quic_rajeevny@quicinc.com>
Signed-off-by: default avatarKrishna Manikandan <quic_mkrishn@quicinc.com>
Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarSankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1640361793-26486-3-git-send-email-quic_sbillaka@quicinc.com
parent fcb68dfd

arch/arm64/boot/dts/qcom/sc7280.dtsi

+109 −2
Original line number Diff line number Diff line
@@ -2766,8 +2766,14 @@ dispcc: clock-controller@af00000 { 
			reg = <0 0xaf00000 0 0x20000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,

				 <0>, <0>, <0>, <0>, <0>, <0>;

			clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",

				 <&mdss_dsi_phy 0>,

				 <&mdss_dsi_phy 1>,

				 <0>,

				 <0>,

				 <0>,

				 <0>;

			clock-names = "bi_tcxo",

				      "gcc_disp_gpll0_clk",

				      "dsi0_phy_pll_out_byteclk",

				      "dsi0_phy_pll_out_dsiclk",

				      "dp_phy_pll_link_clk",
@@ -2843,6 +2849,18 @@ mdss_mdp: display-controller@ae01000 { 


				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						dpu_intf1_out: endpoint {

							remote-endpoint = <&dsi0_in>;

						};

					};

				};



				mdp_opp_table: opp-table {

					compatible = "operating-points-v2";
@@ -2867,6 +2885,95 @@ opp-506666667 { 
					};

				};

			};



			mdss_dsi: dsi@ae94000 {

				compatible = "qcom,mdss-dsi-ctrl";

				reg = <0 0x0ae94000 0 0x400>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <4>;



				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,

					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,

					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,

					 <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&gcc GCC_DISP_HF_AXI_CLK>;

				clock-names = "byte",

					      "byte_intf",

					      "pixel",

					      "core",

					      "iface",

					      "bus";



				operating-points-v2 = <&dsi_opp_table>;

				power-domains = <&rpmhpd SC7280_CX>;



				phys = <&mdss_dsi_phy>;

				phy-names = "dsi";



				#address-cells = <1>;

				#size-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						dsi0_in: endpoint {

							remote-endpoint = <&dpu_intf1_out>;

						};

					};



					port@1 {

						reg = <1>;

						dsi0_out: endpoint {

						};

					};

				};



				dsi_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-187500000 {

						opp-hz = /bits/ 64 <187500000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-300000000 {

						opp-hz = /bits/ 64 <300000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-358000000 {

						opp-hz = /bits/ 64 <358000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};

				};

			};



			mdss_dsi_phy: phy@ae94400 {

				compatible = "qcom,sc7280-dsi-phy-7nm";

				reg = <0 0x0ae94400 0 0x200>,

				      <0 0x0ae94600 0 0x280>,

				      <0 0x0ae94900 0 0x280>;

				reg-names = "dsi_phy",

					    "dsi_phy_lane",

					    "dsi_pll";



				#clock-cells = <1>;

				#phy-cells = <0>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&rpmhcc RPMH_CXO_CLK>;

				clock-names = "iface", "ref";



				status = "disabled";

			};

		};



		pdc: interrupt-controller@b220000 {