Commit 276c03a0 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/smu: Update SMU13 support for SMU 13.0.0 



Modify the common smu13 code and add a new smu
13.0.0 ppt file to handle the smu 13.0.0 specific
configuration.

v2: squash in typo fix in profile name

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce81151c

drivers/gpu/drm/amd/pm/amdgpu_pm.c

+1 −0
Original line number Diff line number Diff line
@@ -1994,6 +1994,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ 
		case IP_VERSION(9, 4, 1):

		case IP_VERSION(9, 4, 2):

		case IP_VERSION(10, 3, 0):

		case IP_VERSION(11, 0, 0):

			*states = ATTR_STATE_SUPPORTED;

			break;

		default:

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+4 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#include "aldebaran_ppt.h"

#include "yellow_carp_ppt.h"

#include "cyan_skillfish_ppt.h"

#include "smu_v13_0_0_ppt.h"

#include "smu_v13_0_5_ppt.h"

#include "amd_pcie.h"
@@ -565,6 +566,9 @@ static int smu_set_funcs(struct amdgpu_device *adev) 
		/* Enable pp_od_clk_voltage node */

		smu->od_enabled = true;

		break;

	case IP_VERSION(13, 0, 0):

		smu_v13_0_0_set_ppt_funcs(smu);

		break;

	default:

		return -EINVAL;

	}

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+6 −0
Original line number Diff line number Diff line
@@ -454,6 +454,7 @@ struct smu_umd_pstate_table { 
	struct pstates_clk_freq		uclk_pstate;

	struct pstates_clk_freq		vclk_pstate;

	struct pstates_clk_freq		dclk_pstate;

	struct pstates_clk_freq		fclk_pstate;

};



struct cmn2asic_msg_mapping {
@@ -1327,6 +1328,8 @@ typedef enum { 
	METRICS_AVERAGE_UCLK,

	METRICS_AVERAGE_VCLK,

	METRICS_AVERAGE_DCLK,

	METRICS_AVERAGE_VCLK1,

	METRICS_AVERAGE_DCLK1,

	METRICS_AVERAGE_GFXACTIVITY,

	METRICS_AVERAGE_MEMACTIVITY,

	METRICS_AVERAGE_VCNACTIVITY,
@@ -1345,6 +1348,9 @@ typedef enum { 
	METRICS_SS_DGPU_SHARE,

	METRICS_UNIQUE_ID_UPPER32,

	METRICS_UNIQUE_ID_LOWER32,

	METRICS_PCIE_RATE,

	METRICS_PCIE_WIDTH,

	METRICS_CURR_FANPWM,

} MetricsMember_t;



enum smu_cmn2asic_mapping_type {

drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h

+2 −0
Original line number Diff line number Diff line
@@ -366,6 +366,8 @@ enum smu_clk_type { 
       __SMU_DUMMY_MAP(THM_CG),				\

       __SMU_DUMMY_MAP(CLK_CG),				\

       __SMU_DUMMY_MAP(DATA_CALCULATION),				\

       __SMU_DUMMY_MAP(DPM_VCLK),			\

       __SMU_DUMMY_MAP(DPM_DCLK),			\



#undef __SMU_DUMMY_MAP

#define __SMU_DUMMY_MAP(feature)	SMU_FEATURE_##feature##_BIT

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

+16 −13
Original line number Diff line number Diff line
@@ -28,9 +28,10 @@ 
#define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF

#define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04

#define SMU13_DRIVER_IF_VERSION_ALDE 0x08

#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04

#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x27



#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms

#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04



/* MP Apertures */

#define MP0_Public			0x03800000
@@ -49,7 +50,7 @@ 
#define SMU13_TOOL_SIZE			0x19000



#define MAX_DPM_LEVELS 16

#define MAX_PCIE_CONF 2

#define MAX_PCIE_CONF 3



#define CTF_OFFSET_EDGE			5

#define CTF_OFFSET_HOTSPOT		5
@@ -73,12 +74,15 @@ struct smu_13_0_dpm_table { 
	uint32_t			min;        /* MHz */

	uint32_t			max;        /* MHz */

	uint32_t			count;

	bool				is_fine_grained;

	struct smu_13_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];

};



struct smu_13_0_pcie_table {

	uint8_t  pcie_gen[MAX_PCIE_CONF];

	uint8_t  pcie_lane[MAX_PCIE_CONF];

	uint16_t clk_freq[MAX_PCIE_CONF];

	uint32_t num_of_link_levels;

};



struct smu_13_0_dpm_tables {
@@ -192,8 +196,8 @@ int 
smu_v13_0_set_fan_control_mode(struct smu_context *smu,

			       uint32_t mode);



int

smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);

int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,

				uint32_t speed);



int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,

				uint32_t speed);
@@ -238,15 +242,6 @@ int smu_v13_0_set_performance_level(struct smu_context *smu, 
int smu_v13_0_set_power_source(struct smu_context *smu,

			       enum smu_power_src_type power_src);



int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,

				    enum smu_clk_type clk_type,

				    uint16_t level,

				    uint32_t *value);



int smu_v13_0_get_dpm_level_count(struct smu_context *smu,

				  enum smu_clk_type clk_type,

				  uint32_t *value);



int smu_v13_0_set_single_dpm_table(struct smu_context *smu,

				   enum smu_clk_type clk_type,

				   struct smu_13_0_dpm_table *single_dpm_table);
@@ -270,5 +265,13 @@ int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 
int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,

			     uint64_t event_arg);



int smu_v13_0_set_vcn_enable(struct smu_context *smu,

			     bool enable);



int smu_v13_0_set_jpeg_enable(struct smu_context *smu,

			      bool enable);



int smu_v13_0_init_pptable_microcode(struct smu_context *smu);



#endif

#endif