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Unverified Commit 2bc3fc87 authored by Anup Patel's avatar Anup Patel Committed by Palmer Dabbelt
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RISC-V: Remove CLINT related code from timer and arch



Right now the RISC-V timer driver is convoluted to support:
1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for
   clocksource and SBI timer calls for clockevent device.
2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO
   counter register for clocksource and CLINT MMIO compare register
   for clockevent device.

We now have a separate CLINT timer driver which also provide CLINT
based IPI operations so let's remove CLINT MMIO related code from
arch/riscv directory and RISC-V timer driver.

Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
Tested-by: default avatarEmil Renner Berhing <kernel@esmil.dk>
Acked-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: default avatarAtish Patra <atish.patra@wdc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 2ac6795f
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