ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs

According to [0] pointed out by Marc Zyngier in a report about a
similar error message, PPIs 11 and 13 are edge triggered on
Cortex-A9 socs including the rk3066 and rk3188 which currently
mark them as level triggered.

Until some time ago the gic did not care but commit 992345a5
("irqchip/gic: WARN if setting the interrupt type for a PPI fails")
introduced a warning for that case.

Fix the warning on these socs by describing the interrupts correctly
and also using the binding constants for easier reading in the future.

[0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html



Signed-off-by: Heiko Stuebner <heiko@sntech.de>