Commit 32e8ab05 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Update SW state correctly for FCLK 



FCLK not supported for DCN321, but still need to update the software
state accordingly to prevent unneeded full updates in driver

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a3a88587

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+3 −3
Original line number Diff line number Diff line
@@ -431,12 +431,12 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 
						clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);

		}



		if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&

				should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {

		if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&

				clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) {

			clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;



			/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */

			if (!clk_mgr_base->clks.fclk_p_state_change_support) {

			if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support) {

				/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */

				dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);

			}