Commit 354065be authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Nishanth Menon
Browse files

arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES 



AM642 EVM has a x4 lane PCIe connector. Enable PCIe in RC mode here.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: default avatarAswath Govindraju <a-govindraju@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603142251.14563-4-kishon@ti.com
parent 4a868bff

arch/arm64/boot/dts/ti/k3-am642-evm.dts

+30 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 


/dts-v1/;



#include <dt-bindings/phy/phy.h>

#include <dt-bindings/mux/ti-serdes.h>

#include <dt-bindings/leds/common.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/net/ti-dp83867.h>
@@ -466,3 +468,31 @@ mbox_m4_0: mbox-m4-0 { 
&mailbox0_cluster7 {

	status = "disabled";

};



&serdes_ln_ctrl {

	idle-states = <AM64_SERDES0_LANE0_PCIE0>;

};



&serdes0 {

	serdes0_pcie_link: phy@0 {

		reg = <0>;

		cdns,num-lanes = <1>;

		#phy-cells = <0>;

		cdns,phy-type = <PHY_TYPE_PCIE>;

		resets = <&serdes_wiz0 1>;

	};

};



&pcie0_rc {

	reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;

	phys = <&serdes0_pcie_link>;

	phy-names = "pcie-phy";

	num-lanes = <1>;

};



&pcie0_ep {

	phys = <&serdes0_pcie_link>;

	phy-names = "pcie-phy";

	num-lanes = <1>;

	status = "disabled";

};