Commit 36de991e authored by Dinh Nguyen's avatar Dinh Nguyen
Browse files

ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" 



Because of commit 9cb2ff11 ("spi: cadence-quadspi: Disable Auto-HW polling"),
which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register
regardless of any condition. Well, the Cadence QuadSPI controller on
Intel's SoCFPGA platforms does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash!

So starting with v5.16, I introduced the patch
98d948eb ("spi: cadence-quadspi: fix write completion support"),
which adds the dts compatible "intel,socfpga-qspi" that is specific for
versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.

Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
---
v3: revert back to "intel,socfpga-qspi"
v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010"
parent f34e8875

arch/arm/boot/dts/socfpga.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -782,7 +782,7 @@ ocram: sram@ffff0000 { 
		};



		qspi: spi@ff705000 {

			compatible = "cdns,qspi-nor";

			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0xff705000 0x1000>,

arch/arm/boot/dts/socfpga_arria10.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -756,7 +756,7 @@ usb0-ecc@ff8c8800 { 
		};



		qspi: spi@ff809000 {

			compatible = "cdns,qspi-nor";

			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0xff809000 0x100>,

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -594,7 +594,7 @@ emac0-tx-ecc@ff8c0400 { 
		};



		qspi: spi@ff8d2000 {

			compatible = "cdns,qspi-nor";

			compatible =  "intel,socfpga-qspi", "cdns,qspi-nor";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0xff8d2000 0x100>,

arch/arm64/boot/dts/intel/socfpga_agilex.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -628,7 +628,7 @@ sdmmca-ecc@ff8c8c00 { 
		};



		qspi: spi@ff8d2000 {

			compatible = "cdns,qspi-nor";

			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0xff8d2000 0x100>,